[LLVMdev] adjust address calculus for an architecture that does not address bytes

[Richard Osborne]

Christian Sayer wrote:
> Hi,
> my target architecture has a kind of "16bit addressing mode", i.e. one address does not address 8 bit but a 16bit chunk. Consequently, every constant used to calculate effective addresses must be divided by two.
> So far this is not such a problem for stack objects since FrameIndexes, function arguments etc. have a lot of custom lowering code where this can be done.
> But when it comes to pointer arithmetic resulting from the GetElementPtr instruction this is less obvious.
> At first I thought this could be handled when lowering loads and stores, but I realize that I can only catch the targeted addresses of loads/stores here - however address calculation nodes may occur anywhere in a DAG.
>
> So my first impulse would be to adjust the constants when the GEP instructions are transformed to ADDs. Afaics his would mean to change the TargetData class, which is not meant to be subclassed.
> Is there a cleaner solution without modifying llvm?
>
> Regards, Christian
The XCore has loads / stores where the offset is scaled by the size of 
the load or store. For example the load word instruction LDW takes an 
offset which is multiplied by 4 and added to the base pointer. This is 
dealt with in the patterns defined in XCoreInstrInfo.td. The following 
pattern is used for LDW:

def : Pat<(load (add GRRegs:$addr, immUs4:$offset)),
          (LDW_2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;

immUs4 is true when offset is a multiple of 4 and the offset divided by 
4 fits in an immediate. The div4_xform xform divides a constant by 4. 
These are both defined in XCoreInstrInfo.td.

It sounds like your target may be able to use a similar approach.

-- 
Richard Osborne | XMOS
http://www.xmos.com