[LLVMdev] SSE examples

Chris Lattner clattner at apple.com
Mon Jun 22 16:44:28 PDT 2009

On Jun 22, 2009, at 1:54 PM, Jon Harrop wrote:

> On Monday 22 June 2009 16:37:41 BGB wrote:
>> as for what targets support which operations, in the case of SSE,  
>> go check
>> the Intel and AMD64 docs.
> I was assuming that LLVM's implementations were incomplete. Are they  
> now
> complete? So anything that a CPU can do and LLVM has bindings for is
> implemented?

The issue is that most vector ISA's don't implement every operation.   
If SSE (for example) doesn't implement an operation efficiently,  
you'll get inefficient but correct code.


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