[LLVMdev] Tablegen question

Manjunath Kudlur keveman at gmail.com
Sat Jun 6 09:47:08 PDT 2009

I want to add a set of "properties" to each instruction in my
instruction set, and want to be able to query that in my
machine-specific optimizations. My Insts.td file looks as follows :

class InstProperty;

def propX : InstProperty;
def propY : InstProperty;
def propZ : InstProperty;

class myInst<..., list<InstProperty> props> : Instruction {
  list<InstProperty> Properties=props;

def i1 : myInst<..., [propX]>;
def i2 : myInst<..., [propX, propZ]>;
def i3 : myInst<..., []>;

I want to add a Tablegen backend that would look for Instructions
derived from myInst, look for Properties field, and output a
opcode->bitfield map as follows:

PropMap[myInst::i1] = propX;
PropMap[myInst::i2] = propX | propZ;
PropMap[myInst::i3] = 0;

where propX,propY,and propZ will be defined as appropriate enums.
Now, I looked at the current Tablegen backends, and I didn't find any
that are specific to a particular architecture backend, say, to X86 or
Sparc etc.. That got me wondering if I am breaking some conventions
and not doing things in the LLVM-way. Is what I am trying to do an
intended use case for Tablegen? Why aren't there Tablegen backends
specific to some architecture backends? I would be grateful for any
advice from the community.


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