[LLVMdev] Vector logic regression in r73431

[Nicolas Capens]

Hi all,
Hi Eli,

No, that appears to be something unrelated. I'm currently using revision
75246, while that patch only seems to apply to some later revision.

Anyway, I actually located the real bug. Right at the end of
InstCombiner::SimplifyDemandedUseBits, there's this piece of code:

  // If the client is only demanding bits that we know, return the known
  // constant.
  if ((DemandedMask & (RHSKnownZero|RHSKnownOne)) == DemandedMask) {
    Constant *C = Context->getConstantInt(RHSKnownOne);
    if (isa<PointerType>(V->getType()))
      C = Context->getConstantExprIntToPtr(C, V->getType());
    return C;
  }
  return false;
}

Note that C is a scalar integer, and so when V is actually a vector the type
isn't preserved.

I'm not entirely sure how this function is supposed to work with vectors
though. DemandedMask, KnownOne and KnownZero are APInt's (scalars) the size
of an element of the vector. So when, as the comment describes, only known
bits are demanded, does that apply to just one element of the vector or all?

Thanks,

Nicolas


-----Original Message-----
From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On
Behalf Of Eli Friedman
Sent: woensdag 29 juli 2009 20:44
To: LLVM Developers Mailing List
Subject: Re: [LLVMdev] Vector logic regression in r73431

On Wed, Jul 29, 2009 at 3:45 AM, Nicolas Capens<nicolas at capens.net> wrote:
> So could anyone who knows the ins and outs of this code have a look at 
> how to make it handle vectors correctly? Or if that's not an option 
> right now, please revert the broken optimizations. Note that there 
> might be more things affected than visitAnd, visitOr and vistXor, I've 
> only been able to identify these so far with little knowledge of the 
> actual code. I currently don't have a reduced testcase, but if really
necessary I can try to extract one.

Does the attached help?

-Eli