[LLVMdev] Vector logic regression in r73431

[Eli Friedman]

On Wed, Jul 29, 2009 at 3:45 AM, Nicolas Capens<nicolas at capens.net> wrote:
> So could anyone who knows the ins and outs of this code have a look at how
> to make it handle vectors correctly? Or if that’s not an option right now,
> please revert the broken optimizations. Note that there might be more things
> affected than visitAnd, visitOr and vistXor, I’ve only been able to identify
> these so far with little knowledge of the actual code. I currently don’t
> have a reduced testcase, but if really necessary I can try to extract one.

Does the attached help?

-Eli
-------------- next part --------------
Index: InstructionCombining.cpp
===================================================================
--- InstructionCombining.cpp	(revision 77486)
+++ InstructionCombining.cpp	(working copy)
@@ -1014,7 +1014,7 @@
     if ((DemandedMask & (RHSKnownZero|RHSKnownOne)) == DemandedMask) { 
       // all known
       if ((RHSKnownOne & LHSKnownOne) == RHSKnownOne) {
-        Constant *AndC = ConstantInt::get(*Context, 
+        Constant *AndC = ConstantInt::get(VTy, 
                                           ~RHSKnownOne & DemandedMask);
         Instruction *And = 
           BinaryOperator::CreateAnd(I->getOperand(0), AndC, "tmp");
@@ -1407,7 +1407,7 @@
   // If the client is only demanding bits that we know, return the known
   // constant.
   if ((DemandedMask & (RHSKnownZero|RHSKnownOne)) == DemandedMask) {
-    Constant *C = ConstantInt::get(*Context, RHSKnownOne);
+    Constant *C = ConstantInt::get(VTy, RHSKnownOne);
     if (isa<PointerType>(V->getType()))
       C = Context->getConstantExprIntToPtr(C, V->getType());
     return C;