[LLVMdev] SplitVecRes with SIGN_EXTEND_INREG unsupported

Eli Friedman eli.friedman at gmail.com
Thu Dec 10 18:49:50 PST 2009

On Thu, Dec 10, 2009 at 6:40 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote:
> A question that has more impact, should the DAG combiner generate any combination of instructions that it cannot undo? I would say that it shouldn't, and this is a bug in LLVM.
> This is one situation where it generates code that causes it to assert, whereas the original code works if this combination is disabled or only generated on scalar types.
> Idea's?

I'd be fine with simply disabling the transformation in question on vectors.


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