[LLVMdev] SplitVecRes with SIGN_EXTEND_INREG unsupported

[Villmow, Micah]

Ok, It doesn't work. The problem is LLVM then asserts later on in SelectionDAG:2642 because it is checking to see whether the second operand is an Integer, and if not it assumes it is floating point and asserts with the method Cannot *_EXTEND_INREG FP types.

So, it seems that the root problem here is the 'MVT::Other' still hanging around. How do I convert this SDValue to an int vector that LLVM won't complain about?

Thanks,
Micah

> -----Original Message-----
> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu]
> On Behalf Of Villmow, Micah
> Sent: Thursday, December 10, 2009 3:30 PM
> To: llvmdev at cs.uiuc.edu
> Subject: Re: [LLVMdev] SplitVecRes with SIGN_EXTEND_INREG unsupported
> 
> Eli,
>  I think I was able to get it working. Thanks for the help, does this
> look correct to you?
> 
> void DAGTypeLegalizer::SplitVecRes_SIGN_EXTEND_INREG(SDNode *N, SDValue
> &Lo,
>                                          SDValue &Hi) {
>   SDValue LHSLo, LHSHi;
>   GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
>   DebugLoc dl = N->getDebugLoc();
>   EVT LoVT, HiVT;
>   GetSplitDestVTs(N->getValueType(1), LoVT, HiVT);
> 
>   Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
> DAG.getValueType(LoVT));
>   Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,
> DAG.getValueType(HiVT));
> }
> 
> 
> Thanks,
> Micah
> > -----Original Message-----
> > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-
> bounces at cs.uiuc.edu]
> > On Behalf Of Villmow, Micah
> > Sent: Thursday, December 10, 2009 3:10 PM
> > To: llvmdev at cs.uiuc.edu
> > Subject: Re: [LLVMdev] SplitVecRes with SIGN_EXTEND_INREG unsupported
> >
> > Eli,
> >  I don't see how this helps with the splitting of the Other node as
> it
> > isn't the Dest that is the problem, but the second source value. Any
> > place in the code that I can look at on how to split a VTSDNode?
> >
> > Thanks,
> > Micah
> >
> > > -----Original Message-----
> > > From: Eli Friedman [mailto:eli.friedman at gmail.com]
> > > Sent: Thursday, December 10, 2009 1:25 PM
> > > To: Villmow, Micah
> > > Cc: llvmdev at cs.uiuc.edu
> > > Subject: Re: [LLVMdev] SplitVecRes with SIGN_EXTEND_INREG
> unsupported
> > >
> > > On Thu, Dec 10, 2009 at 12:46 PM, Villmow, Micah
> > > <Micah.Villmow at amd.com> wrote:
> > > > Eli,
> > > >  I have a simple SplitVecRes function that implements what you
> > > mentioned, splitting the LHS just as in BinaryOp, but passing
> through
> > > the RHS. The problem is that the second operand is MVT::Other, but
> > when
> > > casted to an VTSDNode reveals that it is a vector length of the
> same
> > > size as the LHS SDValue. This causes a split on the LHS side to
> work
> > > correctly, but then it fails instruction selection because of
> Other.
> > I
> > > have not been able to figure out how to split the MVT::Other node
> > yet,
> > > any idea how to do this?
> > >
> > >
> > > You should be able to split the contained type with
> GetSplitDestVTs,
> > > then recreate the node using SelectionDAG::getValueType(), I think.
> > >
> > > That said, it could possibly be considered a bug in DAGCombine that
> > > the second operand is a vector type; someone want to comment on
> that?
> > >
> > > -Eli
> >
> >
> >
> > _______________________________________________
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> > LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
> 
> 
> 
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