[LLVMdev] Adding multiples-of-8 integer types to MVT

Ken Dyck Ken.Dyck at onsemi.com
Thu Dec 3 10:47:05 PST 2009

On Thursday, December 03, 2009 3:52 AM, Duncan Sands wrote:
> > Would there be any interest/opposition to extending the set 
> of simple 
> > integer types in MVT to include the missing multiples of 8 
> (up to 64
> > bits)? That is: i24, i40, i48, i56?
> the type legalizer would need some work.  Consider an 
> architecture which has a
> 24 bit register.  Then the type legalizer should legalize an 
> i40 by first promoting it to an i48, then expanding that to 
> two lots of i24.

>From what I can tell, this is mostly a matter of making sure that the
lowering tables in TargetLowering are initialized correctly in
computeRegisterProperties(). The rest of it is finding the code that are
bypassing these lowering tables to legalize types.
> Another issue is how vectors of i24 would be represented in 
> memory.  Would successive vector elements be 3 bytes apart or 
> 4 bytes apart?  The current code for vector codegen assumes 
> that vectors are tightly packed (this is already wrong for 
> x86 long double).

FWIW, I would hope they continue to be packed. Otherwise, they would be
very difficult to process efficiently on native 24-bit machines. On
architectures without 24-bit types, I guess it would be up to the
legalizer to generate code to pad them appropriately in a promotion to
an i32 vector.


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