[LLVMdev] GSoC 2009: Auto-vectorization

Stefanus Du Toit stefanus.dutoit at rapidmind.com
Wed Apr 1 07:08:45 PDT 2009

Hi Andreas,

On 31-Mar-09, at 8:27 PM, Andreas Bolka wrote:
> So, initially, I aim at supporting only the simplest loops such as:
>    int a[256], b[256], c[256];
>    for (int i = 0; i < 256; ++i)
>      c[i] = a[i] + b[i];
> My goal is to implement the necessary analyses and transformations to
> turn IR corresponding to such code into IR utilizing vector
> instructions; i.e. the core of the desired result would look like:
>    %va = load <256 x i32>* %a
>    %vb = load <256 x i32>* %b
>    %vc = add <256 x i32> %a, %b
>    store <256 x i32> %vc, <256 x i32>* %c
> After this transformation, the code could be left as is (which would
> generate a fully unrolled vector-add, as long as the vector length
> doesn't exceed the lowering capabilities of the code generator), or
> strip-mined into a loop using fixed-size vectors (preferably
> corresponding to the SIMD register width of the target architecture).

I think the biggest problem with this approach, apart from the fact  
that it doesn't mirror how vectors are typically used today in LLVM,  
is that vectors in LLVM are of fixed size. This is going to severely  
limit the usefulness of this transformation. I think you may be better  
off getting information about vector widths for the architecture (e.g.  
from TargetData) and vectorizing directly with a particular width in  

Overall, this would be a great GSOC project, and I guarantee you would  
get a lot of interest in this :). Good luck!


Stefanus Du Toit <stefanus.dutoit at rapidmind.com>
   RapidMind Inc.
   phone: +1 519 885 5455 x116 -- fax: +1 519 885 1463

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