[LLVMdev] Making Sense of ISel DAG Output

David Greene dag at cray.com
Thu Oct 2 10:42:21 PDT 2008

On Thursday 02 October 2008 11:37, David Greene wrote:

> I'll try ot write a small example and send it in a bit.

Ok, here's what I'm trying to do:

let AddedComplexity = 40 in {
  def : Pat<(v2f64 (vector_shuffle (v2f64 (scalar_to_vector (loadf64 addr:
                                   (v2f64 (scalar_to_vector (loadf64 addr:
	    (SHUFPDrri (v2f64 (MOVSD2PDrm addr:$src1)),
                       (v2f64 (MOVSD2PDrm addr:$src2)),
                       SHUFP_shuffle_mask:$sm)>, Requires<[HasSSE2]>;
} // AddedComplexity

It turns out you can't actually write a pattern like this with tblgen as-is.  
There's a bug where it outputs multiple definitions of some local variables.  
I've patched that here and hope to send it upstream once I get approval.

But let's say you _could_ write such a pattern (because I can).  The input DAG 
looks like this:

            0x391a220: <multiple use>
          0x391c970: v2f64 = scalar_to_vector 0x391a220 srcLineNum= 10
            0x391ac10: <multiple use>
          0x391c8b0: v2f64 = scalar_to_vector 0x391ac10 srcLineNum= 10
          0x3927b10: <multiple use>
        0x3923100: v2f64 = vector_shuffle 0x391c970, 0x391c8b0, 0x3927b10<0,2> 
srcLineNum= 10

The code that gets produced looks like this:

	%reg1071<def> = MOVSD2PDrm %reg1026, 8, %reg1065, 4294967288, Mem:LD(8,8) 
[r66428 + 0]LD(8,8) [r78427 + 0]	 ; srcLine 10
	%reg1072<def> = MOVSD2PDrm %reg1026, 8, %reg1065, 4294967288, Mem:LD(8,8) 
[r66428 + 0]LD(8,8) [r78427 + 0]	 ; srcLine 10
	%reg1073<def> = SHUFPDrri %reg1071, %reg1072, 0	 ; srcLine 10

Note that %reg1026 and %reg1065 are used in both address expressions even 
though I specified different names ($src1 and $src2) in the pattern.  Huh?  
How do I find out who is screwing up?  It could be an incorrect pattern, it 
could be an incorrectly patched tblgen or it could be somewhere in 
SelectionDAG itself.


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