[LLVMdev] PowerPC instruction cache invalidation

[Gary Benson]

Hi all,

When you genetate code on PowerPC you need to explicitly invalidate
the instruction cache to force the processor to reread it.  In LLVM
there is code to do this for function stubs on Macintosh, but not
for other platforms and not for JITted code generally.

The attached patch adds support for GNU platforms, but I can't figure
out a nice way to call it for all generated code.  Can anyone help?

Cheers,
Gary

-- 
http://gbenson.net/
-------------- next part --------------
--- lib/Target/PowerPC/PPCJITInfo.cpp.orig	2008-06-11 07:12:39
+++ lib/Target/PowerPC/PPCJITInfo.cpp	2008-06-16 08:42:25
@@ -336,6 +336,20 @@
 #if (defined(__POWERPC__) || defined (__ppc__) || defined(_POWER)) && \
 defined(__APPLE__)
   sys_icache_invalidate(Addr, len);
+#elif defined(__GNUC__)
+  const size_t LineSize = 32;
+  
+  const intptr_t Mask = ~(LineSize - 1);
+  const intptr_t StartLine = ((intptr_t) Addr) & Mask;
+  const intptr_t EndLine = ((intptr_t) Addr + len + LineSize - 1) & Mask;
+
+  for (intptr_t Line = StartLine; Line < EndLine; Line += LineSize)
+      asm volatile("dcbf 0, %0" : : "r"(Line));
+  asm volatile("sync");
+
+  for (intptr_t Line = StartLine; Line < EndLine; Line += LineSize)
+      asm volatile("icbi 0, %0" : : "r"(Line));
+  asm volatile("isync");
 #endif
 }