[LLVMdev] Regarding ARM CodeGen

[Gordon Henriksen]

On 2008-07-15, at 14:55, kapil anand wrote:

> I am trying to represent ARM instruction in LLVM. In ARM ISA, PC is  
> itself a General Purpose Register and we can have following kind of  
> instruction
>
> R3 = ADD PC, R2
>
> But it seems that this kind of operation is not possible and my  
> assumption is not correct. Is there any way to represent this kind  
> of operation in LLVM?

Sure, but what are you attempting to implement with this device?

— Gordon