[LLVMdev] Regarding ARM CodeGen

Eli Friedman eli.friedman at gmail.com
Tue Jul 15 16:11:03 PDT 2008


On Tue, Jul 15, 2008 at 11:55 AM, kapil anand <kapilanand2 at gmail.com> wrote:
> Hi Gordon,
>
> I am trying to represent ARM instruction in LLVM. In ARM ISA, PC is itself a
> General Purpose Register and we can have following kind of instruction
>
> R3 = ADD PC, R2
>
> Since label in LLVM corresponds to current position and thus is like a
> logical Program Counter. I was trying to implement the above instruction by
> using label as an arguement to LLVM Add instruction, based on the
> assumption that LLVM CodeGen will finally take care of PC mapping
> accordingly.
>
> label: %tmp3 = add %label,%tmp2
>
> But it seems that this kind of operation is not possible and my assumption
> is not correct. Is there any way to represent this kind of operation in
> LLVM?

You're going about this the wrong way. The question shouldn't be "How
can I represent my instruction in LLVM?", but rather "My architecture
has an interesting instruction X; how can I make LLVM use instruction
X to generate faster code?".  To that end, what sort of high-level
construct are you getting sub-optimal code for?

Off the top of my head, I can think of a few possibilities for this
instruction to speed up switch statements: to shrink jump tables, to
reduce relocations in jump tables, or to allow jump tables in PIC code
to avoid loading the current value of the program counter.  This is
all low-level enough that it belongs in CodeGen, not in the IL.

See http://llvm.org/docs/CodeGenerator.html for documentation on how
code generation works.  And if you haven't already, you might want to
look at some other pages at http://llvm.org/docs/ to get a better feel
for how LLVM works.

-Eli



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