[LLVMdev] Quad precision registers

Fernando Magno Quintao Pereira fernando at CS.UCLA.EDU
Sun Jan 27 14:40:42 PST 2008

Hi, guys.

     I was browsing through SparcRegisterInfo.td, and I did not find 
support for quad-precision floating-point registers, that is, a single 
register of 128 bits aliasing four registers of 32. As this is predicted 
in the Sparc V8 manual (http://www.sparc.org/standards/V8.pdf, page 33), 
do you guys plan on adding this feature?

all the best,


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