[LLVMdev] Quad precision registers

[Chris Lattner]

On Jan 27, 2008, at 2:40 PM, Fernando Magno Quintao Pereira wrote:
>     I was browsing through SparcRegisterInfo.td, and I did not find
> support for quad-precision floating-point registers, that is, a single
> register of 128 bits aliasing four registers of 32. As this is  
> predicted
> in the Sparc V8 manual (http://www.sparc.org/standards/V8.pdf, page  
> 33),
> do you guys plan on adding this feature?

This should be really easy to add support for, but we don't have an  
active sparc maintainer.

-Chris