[LLVMdev] bitconvert for multi-typed RegisterClasses

Evan Cheng evan.cheng at apple.com
Mon Feb 12 10:58:00 PST 2007

On Feb 12, 2007, at 1:41 AM, Christopher Lamb wrote:

> selector refused to select certain ops (specifically stores) for some
> instructions when the operand type wasn't the first type for the
> register class. After some digging around I seem to have solved the
> problem by creating bitconvert patterns between the types in the
> register class like the following:
> def : Pat<(type1 (bitconvert (type2 MR:$src))), (type1 MR:$src)>;
> def : Pat<(type2 (bitconvert (type1 MR:$src))), (type2 MR:$src)>;
> ...
> Adding these patterns appeared to allow the instruction selector to
> select/legalize the store operations. So I have two questions:
> 1) Is relying on these patterns for instruction selection/
> legalization the correct way to implement multi-typed
> RegisterClasses? I like having TableGen do the pattern work for me
> rather than writing custom selection code...
> 2) I'd think that when a multi-typed RegisterClass is declared that
> these bitconvert patterns between types in that class automatically
> become legal. Is there a reason that TableGen shouldn't automatically
> generate these patterns when a multi-typed register class is created?

X86 backend has the VR64 and VR128 register classes which are exactly  
like this. Rather than adding a whole bunch of instruction selection  
rules to match all the possibilities. We've decided to ask the  
legalizer to normalize the target-independent nodes to one particular  
type. See X86ISelLowering.cpp:

     // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
     for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned) 
MVT::v2i64; VT++) {
       setOperationAction(ISD::AND,    (MVT::ValueType)VT, Promote);
       AddPromotedToType (ISD::AND,    (MVT::ValueType)VT, MVT::v2i64);


> Thanks
> --
> Christopher Lamb
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