[LLVMdev] bitconvert for multi-typed RegisterClasses

Christopher Lamb christopher.lamb at gmail.com
Mon Feb 12 01:41:54 PST 2007

Hi All,

I'm working on a back end for an architecture that makes use of multi- 
typed register classes.

def MR: RegisterClass<"namespace", [type1, type2, ... ], ... >

When running some preliminary tests I found that the instruction  
selector refused to select certain ops (specifically stores) for some  
instructions when the operand type wasn't the first type for the  
register class. After some digging around I seem to have solved the  
problem by creating bitconvert patterns between the types in the  
register class like the following:

def : Pat<(type1 (bitconvert (type2 MR:$src))), (type1 MR:$src)>;
def : Pat<(type2 (bitconvert (type1 MR:$src))), (type2 MR:$src)>;

Adding these patterns appeared to allow the instruction selector to  
select/legalize the store operations. So I have two questions:

1) Is relying on these patterns for instruction selection/ 
legalization the correct way to implement multi-typed  
RegisterClasses? I like having TableGen do the pattern work for me  
rather than writing custom selection code...

2) I'd think that when a multi-typed RegisterClass is declared that  
these bitconvert patterns between types in that class automatically  
become legal. Is there a reason that TableGen shouldn't automatically  
generate these patterns when a multi-typed register class is created?

Christopher Lamb

More information about the llvm-dev mailing list