[LLVMdev] FP emulation
romixlev at yahoo.com
Tue Oct 10 16:45:34 PDT 2006
--- Andrew Lenharth <andrewl at lenharth.org> wrote:
> > > That is a reasonable way to do it. Another reasonable way would
> > > to lower them in the instruction selector itself though the use
> > > custom expanders. In practice, using instructions with "call
> > in > them instead of lowering to calls may be simpler.
> > Hmm, let me see. Just to check that I understand your proposal
> > correctly:
> > You mean I don't need to define any FP operations as machine
> > instructions at all. Instead, I basically tell that I will expand
> > FP operations myself and then I simply expand them into the
> > sequence of instructions:
> > mov arg1, %d0 // enfore register constraint
> > mov arg2, %d1 // enfore register constraint
> > call __fsub64
> > Is it correct understanding? If yes, how do I explain that
> > are to be passed on the concrete physical registers like %d0 and
> > and result comes on %d0? Do I need to allocate virtual regs for
> > and pre-assign physical regs somehow?
> > Or my be I have to define a new calling convention that would
> > it?
> The Alpha backend does this for division and remainder of integers.
> See AlphaISelLowering.cpp:501 for the lowering to a custom call node,
> then AlphaISelDAGToDAG.cpp:215 for the enforcing of the register
> constraints (copy into/out of physical registers), then
> AlphaInsrInfo.td:476 (JSRs) for the call instruction with special
> register DEF/USE sets to match the calling convention of the library
> Hope that helps.
Yes, it does. Thank you for giving very concrete references. This
implementation for Alpha backend does exactly what I had in mind for
the emulated FP operations on my target. I'll try to do it the same
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