[LLVMdev] FP emulation

Andrew Lenharth andrewl at lenharth.org
Tue Oct 10 08:57:27 PDT 2006

> > That is a reasonable way to do it.  Another reasonable way would be
> > to  lower them in the instruction selector itself though the use of
> > custom  expanders.  In practice, using instructions with "call foo"
> in > them  instead of lowering to calls may be simpler.
> Hmm, let me see. Just to check that I understand your proposal
> correctly:
> You mean I don't need to define any FP operations as machine
> instructions at all. Instead, I basically tell that I will expand all
> FP operations myself and then I simply expand them into the following
> sequence of instructions:
>   mov arg1, %d0 // enfore register constraint
>   mov arg2, %d1 // enfore register constraint
>   call __fsub64
> Is it correct understanding? If yes, how do I explain that arguments
> are to be passed on the concrete physical registers like %d0 and %d1
> and result comes on %d0? Do I need to allocate virtual regs for them
> and pre-assign physical regs somehow?
> Or my be I have to define a new calling convention that would enforce
> it?

The Alpha backend does this for division and remainder of integers.
See AlphaISelLowering.cpp:501 for the lowering to a custom call node,
then AlphaISelDAGToDAG.cpp:215 for the enforcing of the register
constraints (copy into/out of physical registers), then
AlphaInsrInfo.td:476 (JSRs) for the call instruction with special
register DEF/USE sets to match the calling convention of the library

Hope that helps.


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