[LLVMdev] problems with tablegen and namespaces

Rafael EspĂ­ndola rafael.espindola at gmail.com
Mon May 1 07:47:50 PDT 2006

I am trying to write a skeleton of an ARM back end.  I have declared
the following class

class InstARM<dag ops, string asmstr, list<dag> pattern> : Instruction {
  let Namespace = "ARM";

  dag OperandList = ops;
  let AsmString   = asmstr;
  let Pattern = pattern;

and defined three instructions (ldr, str, and mov).

The problem is that, in the generated code, the namespace isn't used
everywhere I expected. For example,  in
ARMAsmPrinter::printInstruction, the PHI instruction doesn't has an
"ARM::" prepended to it. ldr, str and mov have. An ARM namespace is
also missing in ARMGenInstrNames.inc.

Someone with more experience with tablegen knows why it isn't adding
these namesaces to the generated code?


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