[LLVMdev] Soft-float

[Evan Cheng]

>
>> d) Would it be possible with current implementation of soft-float
>> support to map f32/f64 to integer types smaller than i32, e.g. to  
>> i16?
>> I have the impression that it is not necessarily the case, since it
>> would require that f64 is split into 4 parts.
>
> Yes, this should be fine.
>
>>   This question is more about a theoretical possibility. At the  
>> moment
>> my embedded target supports i32 registers. But some embedded systems
>> are still only 16bit, which means that they would need something like
>> this.
>>   I'm wondering, how easy or difficult would it be to support such a
>> mapping to any integer type?
>
> It should be transparently handled by the framework.  Basically, you'd
> get:
>
> f32 -> f64 -> i64 -> 2x i32 -> 4x i16
>
> If you don't add a register class for i32 or i64, but you do have  
> one for
> i16, legalize will already 'expand' them for you.
>

This will probably require a slightly more extensive patch to  
legalizer. The current mechanism assumes either 1->1 or 1->2  
expansion. It also assumes the result of expansion are of legal  
types. That means, you will have to either 1) modify ExpandOp() to  
handle cases which need to be recursively expanded or 2) modify it to  
return a vector of SDOperand's. Solution one is what I would pursue.  
It's not done simply because there isn't a need for it right now. :-)

Evan

>
> -Chris
>
> -- 
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