[LLVMdev] dependence analyzer for machine code?
sabre at nondot.org
Mon Sep 5 09:13:33 PDT 2005
On Mon, 5 Sep 2005, Andrew Lenharth wrote:
> On Mon, 2005-09-05 at 14:45 +0800, Tzu-Chien Chiu wrote:
>> why there is no general dependency analysis for the "machin code"?
>> perhaps it's because the instruction scheduling is only implemented
>> for sparcv9?
> Most backends use the SelectionDAG infastructure to do this kind of
> thing. (Simplifying things a bit) Each basic block is selected to a DAG
> based IR. Then instruction selection is done, which transforms this DAG
> to a DAG with machine instructions as nodes. At this point all
> dependencies are explicit as edges in the graph. The DAG is then
> scheduled to a machine basic block.
> Hope this helps. The PowerPC backend is furthest along in being
> implemented in this way.
FWIW, starting in this week, two projects of interest are being worked on:
1. A real live scheduler for the target independent code generator is
being started, by Jim Laskey.
2. I'm going to be working on autogenerating the instruction selector from
the .td files, which should significantly reduce the amount of C++ code
you have to write for your target. This will also make it harder to
"do things wrong".
Once #2 is complete, I intend to write some real documentation on the code
generator as well. :)
If you're looking at implementing scheduling yourself, and need to find
out if two machine instructions have dependencies, you need to be aware of
whether the instructions have side effects (these properties are exposed
through TargetInstrInfo (e.g. isLoad), and what registers are loaded and
stored by the instruction. The registers are a union of the operand
register in the machine instructions (isUse operands are reads, isDef
operands are written) and the implicit def/use information (see
If you're looking for higher level dependence info in the backend (e.g.
loop carried dependences), you'll need to do some work, we don't have
anything that works out of the box.
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