[LLVMdev] How to partition registers into different RegisterClass?

[Chris Lattner]

On Mon, 25 Jul 2005, Tzu-Chien Chiu wrote:
> def C200 : ConstFpReg<199, "c200">;
>
> def I0 : ConstIntReg<0, "i0">;
> ...
> def I100 : ConstIntReg<100, "i100">;
>
> def R0 : TempReg<0, "r0">;
> def R32 : TempReg<31, "r32">;
>
> def V0 : InputReg<0, "v0">;
> ..
> def V10 : InputReg<9, "v10">;
>
> def O0 : OutputReg<0, "o0">;
> ..
> def O4 : OutputReg<4, "o4">;
>
> def FloatingPointRC : RegisterClass<packed, 128,
>    [R0, R1, R2, ..., R32,
>     C0, C1, ..., C200,
>     V0, ..., V10,
>     O1, O2, O3, O4]> {
>  let Methods = [{
>    iterator allocation_order_end(MachineFunction &MF) const {
>      return end()-(4+10+200); // only TempReg can be allocated
>  }];
> }

> And linearly assigning the read-only registers for each definition of them?

Yes, this is exactly what I meant.

-Chris

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