[llvm] 576d81b - [RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and GPRPair. (#85887)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 20 08:44:28 PDT 2024
Author: Craig Topper
Date: 2024-03-20T08:44:24-07:00
New Revision: 576d81baa5cf1801bae0fd05892be34acde33c6a
URL: https://github.com/llvm/llvm-project/commit/576d81baa5cf1801bae0fd05892be34acde33c6a
DIFF: https://github.com/llvm/llvm-project/commit/576d81baa5cf1801bae0fd05892be34acde33c6a.diff
LOG: [RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and GPRPair. (#85887)
Previously we used memory like we do to move between GPRs and FPR64 with
the D extension on RV32.
We can instead use REG_SEQUENCE/EXTRACT_SUBREG to inform register
allocation how to do the copy without memory.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoD.td
llvm/test/CodeGen/RISCV/double-arith-strict.ll
llvm/test/CodeGen/RISCV/double-arith.ll
llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
llvm/test/CodeGen/RISCV/double-br-fcmp.ll
llvm/test/CodeGen/RISCV/double-calling-conv.ll
llvm/test/CodeGen/RISCV/double-convert-strict.ll
llvm/test/CodeGen/RISCV/double-convert.ll
llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
llvm/test/CodeGen/RISCV/double-fcmp.ll
llvm/test/CodeGen/RISCV/double-imm.ll
llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll
llvm/test/CodeGen/RISCV/double-intrinsics.ll
llvm/test/CodeGen/RISCV/double-isnan.ll
llvm/test/CodeGen/RISCV/double-maximum-minimum.ll
llvm/test/CodeGen/RISCV/double-mem.ll
llvm/test/CodeGen/RISCV/double-previous-failure.ll
llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
llvm/test/CodeGen/RISCV/double-round-conv.ll
llvm/test/CodeGen/RISCV/double-select-fcmp.ll
llvm/test/CodeGen/RISCV/double-select-icmp.ll
llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
llvm/test/CodeGen/RISCV/fastcc-without-f-reg.ll
llvm/test/CodeGen/RISCV/half-convert-strict.ll
llvm/test/CodeGen/RISCV/half-convert.ll
llvm/test/CodeGen/RISCV/pr64645.ll
llvm/test/CodeGen/RISCV/zdinx-asm-constraint.ll
llvm/test/CodeGen/RISCV/zdinx-boundary-check.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 1b8c1434c9f2d9..55ba4949b3ea06 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -1007,7 +1007,44 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
ReplaceNode(Node, Res);
return;
}
+ case RISCVISD::BuildPairF64: {
+ if (!Subtarget->hasStdExtZdinx())
+ break;
+
+ assert(!Subtarget->is64Bit() && "Unexpected subtarget");
+
+ SDValue Ops[] = {
+ CurDAG->getTargetConstant(RISCV::GPRPairRegClassID, DL, MVT::i32),
+ Node->getOperand(0),
+ CurDAG->getTargetConstant(RISCV::sub_gpr_even, DL, MVT::i32),
+ Node->getOperand(1),
+ CurDAG->getTargetConstant(RISCV::sub_gpr_odd, DL, MVT::i32)};
+
+ SDNode *N =
+ CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL, MVT::f64, Ops);
+ ReplaceNode(Node, N);
+ return;
+ }
case RISCVISD::SplitF64: {
+ if (Subtarget->hasStdExtZdinx()) {
+ assert(!Subtarget->is64Bit() && "Unexpected subtarget");
+
+ if (!SDValue(Node, 0).use_empty()) {
+ SDValue Lo = CurDAG->getTargetExtractSubreg(RISCV::sub_gpr_even, DL, VT,
+ Node->getOperand(0));
+ ReplaceUses(SDValue(Node, 0), Lo);
+ }
+
+ if (!SDValue(Node, 1).use_empty()) {
+ SDValue Hi = CurDAG->getTargetExtractSubreg(RISCV::sub_gpr_odd, DL, VT,
+ Node->getOperand(0));
+ ReplaceUses(SDValue(Node, 1), Hi);
+ }
+
+ CurDAG->RemoveDeadNode(Node);
+ return;
+ }
+
if (!Subtarget->hasStdExtZfa())
break;
assert(Subtarget->hasStdExtD() && !Subtarget->is64Bit() &&
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 4bfd4d0386a86c..25f035e6dd9de1 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -17142,9 +17142,7 @@ static MachineBasicBlock *emitReadCounterWidePseudo(MachineInstr &MI,
static MachineBasicBlock *emitSplitF64Pseudo(MachineInstr &MI,
MachineBasicBlock *BB,
const RISCVSubtarget &Subtarget) {
- assert((MI.getOpcode() == RISCV::SplitF64Pseudo ||
- MI.getOpcode() == RISCV::SplitF64Pseudo_INX) &&
- "Unexpected instruction");
+ assert(MI.getOpcode() == RISCV::SplitF64Pseudo && "Unexpected instruction");
MachineFunction &MF = *BB->getParent();
DebugLoc DL = MI.getDebugLoc();
@@ -17154,9 +17152,7 @@ static MachineBasicBlock *emitSplitF64Pseudo(MachineInstr &MI,
Register HiReg = MI.getOperand(1).getReg();
Register SrcReg = MI.getOperand(2).getReg();
- const TargetRegisterClass *SrcRC = MI.getOpcode() == RISCV::SplitF64Pseudo_INX
- ? &RISCV::GPRPairRegClass
- : &RISCV::FPR64RegClass;
+ const TargetRegisterClass *SrcRC = &RISCV::FPR64RegClass;
int FI = MF.getInfo<RISCVMachineFunctionInfo>()->getMoveF64FrameIndex(MF);
TII.storeRegToStackSlot(*BB, MI, SrcReg, MI.getOperand(2).isKill(), FI, SrcRC,
@@ -17181,8 +17177,7 @@ static MachineBasicBlock *emitSplitF64Pseudo(MachineInstr &MI,
static MachineBasicBlock *emitBuildPairF64Pseudo(MachineInstr &MI,
MachineBasicBlock *BB,
const RISCVSubtarget &Subtarget) {
- assert((MI.getOpcode() == RISCV::BuildPairF64Pseudo ||
- MI.getOpcode() == RISCV::BuildPairF64Pseudo_INX) &&
+ assert(MI.getOpcode() == RISCV::BuildPairF64Pseudo &&
"Unexpected instruction");
MachineFunction &MF = *BB->getParent();
@@ -17193,9 +17188,7 @@ static MachineBasicBlock *emitBuildPairF64Pseudo(MachineInstr &MI,
Register LoReg = MI.getOperand(1).getReg();
Register HiReg = MI.getOperand(2).getReg();
- const TargetRegisterClass *DstRC =
- MI.getOpcode() == RISCV::BuildPairF64Pseudo_INX ? &RISCV::GPRPairRegClass
- : &RISCV::FPR64RegClass;
+ const TargetRegisterClass *DstRC = &RISCV::FPR64RegClass;
int FI = MF.getInfo<RISCVMachineFunctionInfo>()->getMoveF64FrameIndex(MF);
MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(MF, FI);
@@ -17716,10 +17709,8 @@ RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
case RISCV::Select_FPR64IN32X_Using_CC_GPR:
return emitSelectPseudo(MI, BB, Subtarget);
case RISCV::BuildPairF64Pseudo:
- case RISCV::BuildPairF64Pseudo_INX:
return emitBuildPairF64Pseudo(MI, BB, Subtarget);
case RISCV::SplitF64Pseudo:
- case RISCV::SplitF64Pseudo_INX:
return emitSplitF64Pseudo(MI, BB, Subtarget);
case RISCV::PseudoQuietFLE_H:
return emitQuietFCMP(MI, BB, RISCV::FLE_H, RISCV::FEQ_H, Subtarget);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
index 9b4f93d55e337b..8efefee383a6a5 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
@@ -524,20 +524,6 @@ let isCall = 0, mayLoad = 0, mayStore = 1, Size = 8, isCodeGenOnly = 1 in
def PseudoRV32ZdinxSD : Pseudo<(outs), (ins GPRPair:$rs2, GPRNoX0:$rs1, simm12:$imm12), []>;
def : Pat<(store (f64 GPRPair:$rs2), (AddrRegImmINX (XLenVT GPR:$rs1), simm12:$imm12)),
(PseudoRV32ZdinxSD GPRPair:$rs2, GPR:$rs1, simm12:$imm12)>;
-
-/// Pseudo-instructions needed for the soft-float ABI with RV32D
-
-// Moves two GPRs to an FPR.
-let usesCustomInserter = 1 in
-def BuildPairF64Pseudo_INX
- : Pseudo<(outs FPR64IN32X:$dst), (ins GPR:$src1, GPR:$src2),
- [(set FPR64IN32X:$dst, (RISCVBuildPairF64 GPR:$src1, GPR:$src2))]>;
-
-// Moves an FPR to two GPRs.
-let usesCustomInserter = 1 in
-def SplitF64Pseudo_INX
- : Pseudo<(outs GPR:$dst1, GPR:$dst2), (ins FPR64IN32X:$src),
- [(set GPR:$dst1, GPR:$dst2, (RISCVSplitF64 FPR64IN32X:$src))]>;
} // Predicates = [HasStdExtZdinx, IsRV32]
let Predicates = [HasStdExtD] in {
diff --git a/llvm/test/CodeGen/RISCV/double-arith-strict.ll b/llvm/test/CodeGen/RISCV/double-arith-strict.ll
index 186175537772b5..23336933abff98 100644
--- a/llvm/test/CodeGen/RISCV/double-arith-strict.ll
+++ b/llvm/test/CodeGen/RISCV/double-arith-strict.ll
@@ -24,21 +24,7 @@ define double @fadd_d(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fadd_d:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a2
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fadd_d:
@@ -76,21 +62,7 @@ define double @fsub_d(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fsub_d:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fsub.d a0, a0, a2
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fsub_d:
@@ -128,21 +100,7 @@ define double @fmul_d(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fmul_d:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fmul.d a0, a0, a2
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fmul_d:
@@ -180,21 +138,7 @@ define double @fdiv_d(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fdiv_d:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fdiv.d a0, a0, a2
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fdiv_d:
@@ -232,17 +176,7 @@ define double @fsqrt_d(double %a) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fsqrt_d:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fsqrt.d a0, a0
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fsqrt_d:
@@ -398,25 +332,7 @@ define double @fmadd_d(double %a, double %b, double %c) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fmadd_d:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fmadd.d a0, a0, a2, a4
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fmadd_d:
@@ -463,27 +379,9 @@ define double @fmsub_d(double %a, double %b, double %c) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fmsub_d:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.d.w a6, zero
; RV32IZFINXZDINX-NEXT: fadd.d a4, a4, a6
; RV32IZFINXZDINX-NEXT: fmsub.d a0, a0, a2, a4
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fmsub_d:
@@ -572,28 +470,10 @@ define double @fnmadd_d(double %a, double %b, double %c) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fnmadd_d:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.d.w a6, zero
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a6
; RV32IZFINXZDINX-NEXT: fadd.d a4, a4, a6
; RV32IZFINXZDINX-NEXT: fnmadd.d a0, a0, a2, a4
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fnmadd_d:
@@ -701,28 +581,10 @@ define double @fnmadd_d_2(double %a, double %b, double %c) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fnmadd_d_2:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.d.w a6, zero
; RV32IZFINXZDINX-NEXT: fadd.d a2, a2, a6
; RV32IZFINXZDINX-NEXT: fadd.d a4, a4, a6
; RV32IZFINXZDINX-NEXT: fnmadd.d a0, a2, a0, a4
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fnmadd_d_2:
@@ -829,27 +691,9 @@ define double @fnmsub_d(double %a, double %b, double %c) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fnmsub_d:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.d.w a6, zero
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a6
; RV32IZFINXZDINX-NEXT: fnmsub.d a0, a0, a2, a4
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fnmsub_d:
@@ -932,27 +776,9 @@ define double @fnmsub_d_2(double %a, double %b, double %c) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fnmsub_d_2:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.d.w a6, zero
; RV32IZFINXZDINX-NEXT: fadd.d a2, a2, a6
; RV32IZFINXZDINX-NEXT: fnmsub.d a0, a2, a0, a4
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fnmsub_d_2:
diff --git a/llvm/test/CodeGen/RISCV/double-arith.ll b/llvm/test/CodeGen/RISCV/double-arith.ll
index 82ddf06187d383..a2093f5b5e43ad 100644
--- a/llvm/test/CodeGen/RISCV/double-arith.ll
+++ b/llvm/test/CodeGen/RISCV/double-arith.ll
@@ -25,21 +25,7 @@ define double @fadd_d(double %a, double %b) nounwind {
;
; RV32IZFINXZDINX-LABEL: fadd_d:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a2
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fadd_d:
@@ -76,21 +62,7 @@ define double @fsub_d(double %a, double %b) nounwind {
;
; RV32IZFINXZDINX-LABEL: fsub_d:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fsub.d a0, a0, a2
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fsub_d:
@@ -127,21 +99,7 @@ define double @fmul_d(double %a, double %b) nounwind {
;
; RV32IZFINXZDINX-LABEL: fmul_d:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fmul.d a0, a0, a2
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fmul_d:
@@ -178,21 +136,7 @@ define double @fdiv_d(double %a, double %b) nounwind {
;
; RV32IZFINXZDINX-LABEL: fdiv_d:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fdiv.d a0, a0, a2
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fdiv_d:
@@ -231,17 +175,7 @@ define double @fsqrt_d(double %a) nounwind {
;
; RV32IZFINXZDINX-LABEL: fsqrt_d:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fsqrt.d a0, a0
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fsqrt_d:
@@ -280,21 +214,7 @@ define double @fsgnj_d(double %a, double %b) nounwind {
;
; RV32IZFINXZDINX-LABEL: fsgnj_d:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fsgnj.d a0, a0, a2
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fsgnj_d:
@@ -335,15 +255,9 @@ define i32 @fneg_d(double %a, double %b) nounwind {
;
; RV32IZFINXZDINX-LABEL: fneg_d:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a0
; RV32IZFINXZDINX-NEXT: fneg.d a2, a0
; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a2
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fneg_d:
@@ -401,21 +315,7 @@ define double @fsgnjn_d(double %a, double %b) nounwind {
;
; RV32IZFINXZDINX-LABEL: fsgnjn_d:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fsgnjn.d a0, a0, a2
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fsgnjn_d:
@@ -464,23 +364,9 @@ define double @fabs_d(double %a, double %b) nounwind {
;
; RV32IZFINXZDINX-LABEL: fabs_d:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a2
; RV32IZFINXZDINX-NEXT: fabs.d a2, a0
; RV32IZFINXZDINX-NEXT: fadd.d a0, a2, a0
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fabs_d:
@@ -532,21 +418,7 @@ define double @fmin_d(double %a, double %b) nounwind {
;
; RV32IZFINXZDINX-LABEL: fmin_d:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a2
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fmin_d:
@@ -585,21 +457,7 @@ define double @fmax_d(double %a, double %b) nounwind {
;
; RV32IZFINXZDINX-LABEL: fmax_d:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a2
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fmax_d:
@@ -638,25 +496,7 @@ define double @fmadd_d(double %a, double %b, double %c) nounwind {
;
; RV32IZFINXZDINX-LABEL: fmadd_d:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fmadd.d a0, a0, a2, a4
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fmadd_d:
@@ -702,27 +542,9 @@ define double @fmsub_d(double %a, double %b, double %c) nounwind {
;
; RV32IZFINXZDINX-LABEL: fmsub_d:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.d.w a6, zero
; RV32IZFINXZDINX-NEXT: fadd.d a4, a4, a6
; RV32IZFINXZDINX-NEXT: fmsub.d a0, a0, a2, a4
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fmsub_d:
@@ -811,28 +633,10 @@ define double @fnmadd_d(double %a, double %b, double %c) nounwind {
;
; RV32IZFINXZDINX-LABEL: fnmadd_d:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.d.w a6, zero
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a6
; RV32IZFINXZDINX-NEXT: fadd.d a4, a4, a6
; RV32IZFINXZDINX-NEXT: fnmadd.d a0, a0, a2, a4
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fnmadd_d:
@@ -940,28 +744,10 @@ define double @fnmadd_d_2(double %a, double %b, double %c) nounwind {
;
; RV32IZFINXZDINX-LABEL: fnmadd_d_2:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.d.w a6, zero
; RV32IZFINXZDINX-NEXT: fadd.d a2, a2, a6
; RV32IZFINXZDINX-NEXT: fadd.d a4, a4, a6
; RV32IZFINXZDINX-NEXT: fnmadd.d a0, a2, a0, a4
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fnmadd_d_2:
@@ -1060,27 +846,9 @@ define double @fnmadd_d_3(double %a, double %b, double %c) nounwind {
;
; RV32IZFINXZDINX-LABEL: fnmadd_d_3:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fmadd.d a0, a0, a2, a4
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
; RV32IZFINXZDINX-NEXT: lui a2, 524288
; RV32IZFINXZDINX-NEXT: xor a1, a1, a2
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fnmadd_d_3:
@@ -1127,27 +895,9 @@ define double @fnmadd_nsz(double %a, double %b, double %c) nounwind {
;
; RV32IZFINXZDINX-LABEL: fnmadd_nsz:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fmadd.d a0, a0, a2, a4
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
; RV32IZFINXZDINX-NEXT: lui a2, 524288
; RV32IZFINXZDINX-NEXT: xor a1, a1, a2
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fnmadd_nsz:
@@ -1202,27 +952,9 @@ define double @fnmsub_d(double %a, double %b, double %c) nounwind {
;
; RV32IZFINXZDINX-LABEL: fnmsub_d:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.d.w a6, zero
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a6
; RV32IZFINXZDINX-NEXT: fnmsub.d a0, a0, a2, a4
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fnmsub_d:
@@ -1305,27 +1037,9 @@ define double @fnmsub_d_2(double %a, double %b, double %c) nounwind {
;
; RV32IZFINXZDINX-LABEL: fnmsub_d_2:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.d.w a6, zero
; RV32IZFINXZDINX-NEXT: fadd.d a2, a2, a6
; RV32IZFINXZDINX-NEXT: fnmsub.d a0, a2, a0, a4
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fnmsub_d_2:
@@ -1403,25 +1117,7 @@ define double @fmadd_d_contract(double %a, double %b, double %c) nounwind {
;
; RV32IZFINXZDINX-LABEL: fmadd_d_contract:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fmadd.d a0, a0, a2, a4
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fmadd_d_contract:
@@ -1482,27 +1178,9 @@ define double @fmsub_d_contract(double %a, double %b, double %c) nounwind {
;
; RV32IZFINXZDINX-LABEL: fmsub_d_contract:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.d.w a6, zero
; RV32IZFINXZDINX-NEXT: fadd.d a4, a4, a6
; RV32IZFINXZDINX-NEXT: fmsub.d a0, a0, a2, a4
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fmsub_d_contract:
@@ -1601,29 +1279,11 @@ define double @fnmadd_d_contract(double %a, double %b, double %c) nounwind {
;
; RV32IZFINXZDINX-LABEL: fnmadd_d_contract:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.d.w a6, zero
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a6
; RV32IZFINXZDINX-NEXT: fadd.d a2, a2, a6
; RV32IZFINXZDINX-NEXT: fadd.d a4, a4, a6
; RV32IZFINXZDINX-NEXT: fnmadd.d a0, a0, a2, a4
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fnmadd_d_contract:
@@ -1749,28 +1409,10 @@ define double @fnmsub_d_contract(double %a, double %b, double %c) nounwind {
;
; RV32IZFINXZDINX-LABEL: fnmsub_d_contract:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.d.w a6, zero
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a6
; RV32IZFINXZDINX-NEXT: fadd.d a2, a2, a6
; RV32IZFINXZDINX-NEXT: fnmsub.d a0, a0, a2, a4
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fnmsub_d_contract:
diff --git a/llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll b/llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
index 55bf95a126ac18..99835ff59493fd 100644
--- a/llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
+++ b/llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
@@ -141,21 +141,7 @@ define double @fcopysign_fneg(double %a, double %b) nounwind {
;
; RV32IZFINXZDINX-LABEL: fcopysign_fneg:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fsgnjn.d a0, a0, a2
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64I-LABEL: fcopysign_fneg:
diff --git a/llvm/test/CodeGen/RISCV/double-br-fcmp.ll b/llvm/test/CodeGen/RISCV/double-br-fcmp.ll
index 2c5505edb1fa2a..035228e73c7071 100644
--- a/llvm/test/CodeGen/RISCV/double-br-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/double-br-fcmp.ll
@@ -89,23 +89,13 @@ define void @br_fcmp_oeq(double %a, double %b) nounwind {
;
; RV32IZFINXZDINX-LABEL: br_fcmp_oeq:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw a2, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 4(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 4(sp)
; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a2
; RV32IZFINXZDINX-NEXT: bnez a0, .LBB1_2
; RV32IZFINXZDINX-NEXT: # %bb.1: # %if.else
-; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
; RV32IZFINXZDINX-NEXT: .LBB1_2: # %if.then
+; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
+; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: call abort
;
; RV64IZFINXZDINX-LABEL: br_fcmp_oeq:
@@ -155,23 +145,13 @@ define void @br_fcmp_oeq_alt(double %a, double %b) nounwind {
;
; RV32IZFINXZDINX-LABEL: br_fcmp_oeq_alt:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw a2, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 4(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 4(sp)
; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a2
; RV32IZFINXZDINX-NEXT: bnez a0, .LBB2_2
; RV32IZFINXZDINX-NEXT: # %bb.1: # %if.else
-; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
; RV32IZFINXZDINX-NEXT: .LBB2_2: # %if.then
+; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
+; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: call abort
;
; RV64IZFINXZDINX-LABEL: br_fcmp_oeq_alt:
@@ -218,23 +198,13 @@ define void @br_fcmp_ogt(double %a, double %b) nounwind {
;
; RV32IZFINXZDINX-LABEL: br_fcmp_ogt:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT: sw a2, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 4(sp)
; RV32IZFINXZDINX-NEXT: flt.d a0, a2, a0
; RV32IZFINXZDINX-NEXT: bnez a0, .LBB3_2
; RV32IZFINXZDINX-NEXT: # %bb.1: # %if.else
-; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
; RV32IZFINXZDINX-NEXT: .LBB3_2: # %if.then
+; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
+; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: call abort
;
; RV64IZFINXZDINX-LABEL: br_fcmp_ogt:
@@ -281,23 +251,13 @@ define void @br_fcmp_oge(double %a, double %b) nounwind {
;
; RV32IZFINXZDINX-LABEL: br_fcmp_oge:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT: sw a2, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 4(sp)
; RV32IZFINXZDINX-NEXT: fle.d a0, a2, a0
; RV32IZFINXZDINX-NEXT: bnez a0, .LBB4_2
; RV32IZFINXZDINX-NEXT: # %bb.1: # %if.else
-; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
; RV32IZFINXZDINX-NEXT: .LBB4_2: # %if.then
+; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
+; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: call abort
;
; RV64IZFINXZDINX-LABEL: br_fcmp_oge:
@@ -344,23 +304,13 @@ define void @br_fcmp_olt(double %a, double %b) nounwind {
;
; RV32IZFINXZDINX-LABEL: br_fcmp_olt:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw a2, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 4(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 4(sp)
; RV32IZFINXZDINX-NEXT: flt.d a0, a0, a2
; RV32IZFINXZDINX-NEXT: bnez a0, .LBB5_2
; RV32IZFINXZDINX-NEXT: # %bb.1: # %if.else
-; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
; RV32IZFINXZDINX-NEXT: .LBB5_2: # %if.then
+; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
+; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: call abort
;
; RV64IZFINXZDINX-LABEL: br_fcmp_olt:
@@ -407,23 +357,13 @@ define void @br_fcmp_ole(double %a, double %b) nounwind {
;
; RV32IZFINXZDINX-LABEL: br_fcmp_ole:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw a2, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 4(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 4(sp)
; RV32IZFINXZDINX-NEXT: fle.d a0, a0, a2
; RV32IZFINXZDINX-NEXT: bnez a0, .LBB6_2
; RV32IZFINXZDINX-NEXT: # %bb.1: # %if.else
-; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
; RV32IZFINXZDINX-NEXT: .LBB6_2: # %if.then
+; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
+; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: call abort
;
; RV64IZFINXZDINX-LABEL: br_fcmp_ole:
@@ -474,25 +414,15 @@ define void @br_fcmp_one(double %a, double %b) nounwind {
;
; RV32IZFINXZDINX-LABEL: br_fcmp_one:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw a2, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 4(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 4(sp)
; RV32IZFINXZDINX-NEXT: flt.d a4, a0, a2
; RV32IZFINXZDINX-NEXT: flt.d a0, a2, a0
; RV32IZFINXZDINX-NEXT: or a0, a0, a4
; RV32IZFINXZDINX-NEXT: bnez a0, .LBB7_2
; RV32IZFINXZDINX-NEXT: # %bb.1: # %if.else
-; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
; RV32IZFINXZDINX-NEXT: .LBB7_2: # %if.then
+; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
+; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: call abort
;
; RV64IZFINXZDINX-LABEL: br_fcmp_one:
@@ -545,25 +475,15 @@ define void @br_fcmp_ord(double %a, double %b) nounwind {
;
; RV32IZFINXZDINX-LABEL: br_fcmp_ord:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT: sw a2, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 4(sp)
; RV32IZFINXZDINX-NEXT: feq.d a2, a2, a2
; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a0
; RV32IZFINXZDINX-NEXT: and a0, a0, a2
; RV32IZFINXZDINX-NEXT: bnez a0, .LBB8_2
; RV32IZFINXZDINX-NEXT: # %bb.1: # %if.else
-; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
; RV32IZFINXZDINX-NEXT: .LBB8_2: # %if.then
+; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
+; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: call abort
;
; RV64IZFINXZDINX-LABEL: br_fcmp_ord:
@@ -616,25 +536,15 @@ define void @br_fcmp_ueq(double %a, double %b) nounwind {
;
; RV32IZFINXZDINX-LABEL: br_fcmp_ueq:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw a2, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 4(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 4(sp)
; RV32IZFINXZDINX-NEXT: flt.d a4, a0, a2
; RV32IZFINXZDINX-NEXT: flt.d a0, a2, a0
; RV32IZFINXZDINX-NEXT: or a0, a0, a4
; RV32IZFINXZDINX-NEXT: beqz a0, .LBB9_2
; RV32IZFINXZDINX-NEXT: # %bb.1: # %if.else
-; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
; RV32IZFINXZDINX-NEXT: .LBB9_2: # %if.then
+; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
+; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: call abort
;
; RV64IZFINXZDINX-LABEL: br_fcmp_ueq:
@@ -683,23 +593,13 @@ define void @br_fcmp_ugt(double %a, double %b) nounwind {
;
; RV32IZFINXZDINX-LABEL: br_fcmp_ugt:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw a2, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 4(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 4(sp)
; RV32IZFINXZDINX-NEXT: fle.d a0, a0, a2
; RV32IZFINXZDINX-NEXT: beqz a0, .LBB10_2
; RV32IZFINXZDINX-NEXT: # %bb.1: # %if.else
-; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
; RV32IZFINXZDINX-NEXT: .LBB10_2: # %if.then
+; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
+; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: call abort
;
; RV64IZFINXZDINX-LABEL: br_fcmp_ugt:
@@ -746,23 +646,13 @@ define void @br_fcmp_uge(double %a, double %b) nounwind {
;
; RV32IZFINXZDINX-LABEL: br_fcmp_uge:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw a2, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 4(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 4(sp)
; RV32IZFINXZDINX-NEXT: flt.d a0, a0, a2
; RV32IZFINXZDINX-NEXT: beqz a0, .LBB11_2
; RV32IZFINXZDINX-NEXT: # %bb.1: # %if.else
-; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
; RV32IZFINXZDINX-NEXT: .LBB11_2: # %if.then
+; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
+; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: call abort
;
; RV64IZFINXZDINX-LABEL: br_fcmp_uge:
@@ -809,23 +699,13 @@ define void @br_fcmp_ult(double %a, double %b) nounwind {
;
; RV32IZFINXZDINX-LABEL: br_fcmp_ult:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT: sw a2, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 4(sp)
; RV32IZFINXZDINX-NEXT: fle.d a0, a2, a0
; RV32IZFINXZDINX-NEXT: beqz a0, .LBB12_2
; RV32IZFINXZDINX-NEXT: # %bb.1: # %if.else
-; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
; RV32IZFINXZDINX-NEXT: .LBB12_2: # %if.then
+; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
+; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: call abort
;
; RV64IZFINXZDINX-LABEL: br_fcmp_ult:
@@ -872,23 +752,13 @@ define void @br_fcmp_ule(double %a, double %b) nounwind {
;
; RV32IZFINXZDINX-LABEL: br_fcmp_ule:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT: sw a2, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 4(sp)
; RV32IZFINXZDINX-NEXT: flt.d a0, a2, a0
; RV32IZFINXZDINX-NEXT: beqz a0, .LBB13_2
; RV32IZFINXZDINX-NEXT: # %bb.1: # %if.else
-; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
; RV32IZFINXZDINX-NEXT: .LBB13_2: # %if.then
+; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
+; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: call abort
;
; RV64IZFINXZDINX-LABEL: br_fcmp_ule:
@@ -935,23 +805,13 @@ define void @br_fcmp_une(double %a, double %b) nounwind {
;
; RV32IZFINXZDINX-LABEL: br_fcmp_une:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw a2, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 4(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 4(sp)
; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a2
; RV32IZFINXZDINX-NEXT: beqz a0, .LBB14_2
; RV32IZFINXZDINX-NEXT: # %bb.1: # %if.else
-; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
; RV32IZFINXZDINX-NEXT: .LBB14_2: # %if.then
+; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
+; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: call abort
;
; RV64IZFINXZDINX-LABEL: br_fcmp_une:
@@ -1002,25 +862,15 @@ define void @br_fcmp_uno(double %a, double %b) nounwind {
;
; RV32IZFINXZDINX-LABEL: br_fcmp_uno:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT: sw a2, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 4(sp)
; RV32IZFINXZDINX-NEXT: feq.d a2, a2, a2
; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a0
; RV32IZFINXZDINX-NEXT: and a0, a0, a2
; RV32IZFINXZDINX-NEXT: beqz a0, .LBB15_2
; RV32IZFINXZDINX-NEXT: # %bb.1: # %if.else
-; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
; RV32IZFINXZDINX-NEXT: .LBB15_2: # %if.then
+; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
+; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: call abort
;
; RV64IZFINXZDINX-LABEL: br_fcmp_uno:
diff --git a/llvm/test/CodeGen/RISCV/double-calling-conv.ll b/llvm/test/CodeGen/RISCV/double-calling-conv.ll
index d46256b12052e0..57aaa4c9f74e46 100644
--- a/llvm/test/CodeGen/RISCV/double-calling-conv.ll
+++ b/llvm/test/CodeGen/RISCV/double-calling-conv.ll
@@ -28,21 +28,7 @@ define double @callee_double_inreg(double %a, double %b) nounwind {
;
; RV32IZFINXZDINX-LABEL: callee_double_inreg:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a2
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
%1 = fadd double %a, %b
ret double %1
@@ -106,22 +92,11 @@ define double @callee_double_split_reg_stack(i32 %a, i64 %b, i64 %c, double %d,
;
; RV32IZFINXZDINX-LABEL: callee_double_split_reg_stack:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: lw a0, 16(sp)
-; RV32IZFINXZDINX-NEXT: sw a7, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a5, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a6, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
+; RV32IZFINXZDINX-NEXT: mv a0, a7
+; RV32IZFINXZDINX-NEXT: lw a1, 0(sp)
+; RV32IZFINXZDINX-NEXT: mv a3, a6
+; RV32IZFINXZDINX-NEXT: mv a2, a5
; RV32IZFINXZDINX-NEXT: fadd.d a0, a2, a0
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
%1 = fadd double %d, %e
ret double %1
@@ -190,17 +165,11 @@ define double @callee_double_stack(i64 %a, i64 %b, i64 %c, i64 %d, double %e, do
;
; RV32IZFINXZDINX-LABEL: callee_double_stack:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: lw a0, 24(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 28(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 16(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 20(sp)
-; RV32IZFINXZDINX-NEXT: fadd.d a0, a2, a0
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
+; RV32IZFINXZDINX-NEXT: lw a2, 0(sp)
+; RV32IZFINXZDINX-NEXT: lw a3, 4(sp)
+; RV32IZFINXZDINX-NEXT: fadd.d a0, a2, a0
; RV32IZFINXZDINX-NEXT: ret
%1 = fadd double %e, %f
ret double %1
diff --git a/llvm/test/CodeGen/RISCV/double-convert-strict.ll b/llvm/test/CodeGen/RISCV/double-convert-strict.ll
index 967b119581af1a..13bcafb5ebd136 100644
--- a/llvm/test/CodeGen/RISCV/double-convert-strict.ll
+++ b/llvm/test/CodeGen/RISCV/double-convert-strict.ll
@@ -28,13 +28,7 @@ define float @fcvt_s_d(double %a) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcvt_s_d:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.s.d a0, a0
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_s_d:
@@ -72,13 +66,7 @@ define double @fcvt_d_s(float %a) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcvt_d_s:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
; RV32IZFINXZDINX-NEXT: fcvt.d.s a0, a0
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_d_s:
@@ -116,13 +104,7 @@ define i32 @fcvt_w_d(double %a) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcvt_w_d:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rtz
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_w_d:
@@ -162,13 +144,7 @@ define i32 @fcvt_wu_d(double %a) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcvt_wu_d:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_wu_d:
@@ -210,15 +186,9 @@ define i32 @fcvt_wu_d_multiple_use(double %x, ptr %y) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcvt_wu_d_multiple_use:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz
; RV32IZFINXZDINX-NEXT: seqz a1, a0
; RV32IZFINXZDINX-NEXT: add a0, a0, a1
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_wu_d_multiple_use:
@@ -263,13 +233,7 @@ define double @fcvt_d_w(i32 %a) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcvt_d_w:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
; RV32IZFINXZDINX-NEXT: fcvt.d.w a0, a0
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_d_w:
@@ -309,14 +273,8 @@ define double @fcvt_d_w_load(ptr %p) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcvt_d_w_load:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
; RV32IZFINXZDINX-NEXT: lw a0, 0(a0)
; RV32IZFINXZDINX-NEXT: fcvt.d.w a0, a0
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_d_w_load:
@@ -357,13 +315,7 @@ define double @fcvt_d_wu(i32 %a) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcvt_d_wu:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
; RV32IZFINXZDINX-NEXT: fcvt.d.wu a0, a0
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_d_wu:
@@ -409,14 +361,8 @@ define double @fcvt_d_wu_load(ptr %p) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcvt_d_wu_load:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
; RV32IZFINXZDINX-NEXT: lw a0, 0(a0)
; RV32IZFINXZDINX-NEXT: fcvt.d.wu a0, a0
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_d_wu_load:
@@ -661,13 +607,7 @@ define double @fcvt_d_w_i8(i8 signext %a) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcvt_d_w_i8:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
; RV32IZFINXZDINX-NEXT: fcvt.d.w a0, a0
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_d_w_i8:
@@ -705,13 +645,7 @@ define double @fcvt_d_wu_i8(i8 zeroext %a) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcvt_d_wu_i8:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
; RV32IZFINXZDINX-NEXT: fcvt.d.wu a0, a0
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_d_wu_i8:
@@ -749,13 +683,7 @@ define double @fcvt_d_w_i16(i16 signext %a) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcvt_d_w_i16:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
; RV32IZFINXZDINX-NEXT: fcvt.d.w a0, a0
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_d_w_i16:
@@ -793,13 +721,7 @@ define double @fcvt_d_wu_i16(i16 zeroext %a) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcvt_d_wu_i16:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
; RV32IZFINXZDINX-NEXT: fcvt.d.wu a0, a0
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_d_wu_i16:
diff --git a/llvm/test/CodeGen/RISCV/double-convert.ll b/llvm/test/CodeGen/RISCV/double-convert.ll
index 3700a18bafc612..7a9439e5b322c6 100644
--- a/llvm/test/CodeGen/RISCV/double-convert.ll
+++ b/llvm/test/CodeGen/RISCV/double-convert.ll
@@ -20,13 +20,7 @@ define float @fcvt_s_d(double %a) nounwind {
;
; RV32IZFINXZDINX-LABEL: fcvt_s_d:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.s.d a0, a0
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_s_d:
@@ -63,13 +57,7 @@ define double @fcvt_d_s(float %a) nounwind {
;
; RV32IZFINXZDINX-LABEL: fcvt_d_s:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
; RV32IZFINXZDINX-NEXT: fcvt.d.s a0, a0
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_d_s:
@@ -106,13 +94,7 @@ define i32 @fcvt_w_d(double %a) nounwind {
;
; RV32IZFINXZDINX-LABEL: fcvt_w_d:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rtz
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_w_d:
@@ -153,17 +135,11 @@ define i32 @fcvt_w_d_sat(double %a) nounwind {
;
; RV32IZFINXZDINX-LABEL: fcvt_w_d_sat:
; RV32IZFINXZDINX: # %bb.0: # %start
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.w.d a2, a0, rtz
; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a0
; RV32IZFINXZDINX-NEXT: seqz a0, a0
; RV32IZFINXZDINX-NEXT: addi a0, a0, -1
; RV32IZFINXZDINX-NEXT: and a0, a0, a2
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_w_d_sat:
@@ -287,13 +263,7 @@ define i32 @fcvt_wu_d(double %a) nounwind {
;
; RV32IZFINXZDINX-LABEL: fcvt_wu_d:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_wu_d:
@@ -334,15 +304,9 @@ define i32 @fcvt_wu_d_multiple_use(double %x, ptr %y) nounwind {
;
; RV32IZFINXZDINX-LABEL: fcvt_wu_d_multiple_use:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz
; RV32IZFINXZDINX-NEXT: seqz a1, a0
; RV32IZFINXZDINX-NEXT: add a0, a0, a1
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_wu_d_multiple_use:
@@ -402,17 +366,11 @@ define i32 @fcvt_wu_d_sat(double %a) nounwind {
;
; RV32IZFINXZDINX-LABEL: fcvt_wu_d_sat:
; RV32IZFINXZDINX: # %bb.0: # %start
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.wu.d a2, a0, rtz
; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a0
; RV32IZFINXZDINX-NEXT: seqz a0, a0
; RV32IZFINXZDINX-NEXT: addi a0, a0, -1
; RV32IZFINXZDINX-NEXT: and a0, a0, a2
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_wu_d_sat:
@@ -512,13 +470,7 @@ define double @fcvt_d_w(i32 %a) nounwind {
;
; RV32IZFINXZDINX-LABEL: fcvt_d_w:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
; RV32IZFINXZDINX-NEXT: fcvt.d.w a0, a0
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_d_w:
@@ -557,14 +509,8 @@ define double @fcvt_d_w_load(ptr %p) nounwind {
;
; RV32IZFINXZDINX-LABEL: fcvt_d_w_load:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
; RV32IZFINXZDINX-NEXT: lw a0, 0(a0)
; RV32IZFINXZDINX-NEXT: fcvt.d.w a0, a0
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_d_w_load:
@@ -605,13 +551,7 @@ define double @fcvt_d_wu(i32 %a) nounwind {
;
; RV32IZFINXZDINX-LABEL: fcvt_d_wu:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
; RV32IZFINXZDINX-NEXT: fcvt.d.wu a0, a0
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_d_wu:
@@ -656,14 +596,8 @@ define double @fcvt_d_wu_load(ptr %p) nounwind {
;
; RV32IZFINXZDINX-LABEL: fcvt_d_wu_load:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
; RV32IZFINXZDINX-NEXT: lw a0, 0(a0)
; RV32IZFINXZDINX-NEXT: fcvt.d.wu a0, a0
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_d_wu_load:
@@ -809,13 +743,11 @@ define i64 @fcvt_l_d_sat(double %a) nounwind {
; RV32IZFINXZDINX-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw s0, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw s1, 4(sp)
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI12_0)
; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI12_0+4)(a2)
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI12_0)(a2)
+; RV32IZFINXZDINX-NEXT: mv s1, a1
+; RV32IZFINXZDINX-NEXT: mv s0, a0
; RV32IZFINXZDINX-NEXT: fle.d s2, a2, s0
; RV32IZFINXZDINX-NEXT: neg s3, s2
; RV32IZFINXZDINX-NEXT: call __fixdfdi
@@ -1057,18 +989,17 @@ define i64 @fcvt_lu_d_sat(double %a) nounwind {
;
; RV32IZFINXZDINX-LABEL: fcvt_lu_d_sat:
; RV32IZFINXZDINX: # %bb.0: # %start
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -32
-; RV32IZFINXZDINX-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw s0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw s1, 12(sp)
+; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
+; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT: mv s1, a1
; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero
-; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
-; RV32IZFINXZDINX-NEXT: neg s2, a2
+; RV32IZFINXZDINX-NEXT: mv s0, a0
+; RV32IZFINXZDINX-NEXT: fle.d a0, a2, s0
+; RV32IZFINXZDINX-NEXT: neg s2, a0
+; RV32IZFINXZDINX-NEXT: mv a0, s0
; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI14_0)
; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI14_0+4)(a2)
@@ -1079,11 +1010,11 @@ define i64 @fcvt_lu_d_sat(double %a) nounwind {
; RV32IZFINXZDINX-NEXT: or a0, a2, a0
; RV32IZFINXZDINX-NEXT: and a1, s2, a1
; RV32IZFINXZDINX-NEXT: or a1, a2, a1
-; RV32IZFINXZDINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 32
+; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZFINXZDINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZFINXZDINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
+; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_lu_d_sat:
@@ -1186,14 +1117,6 @@ define i64 @fmv_x_d(double %a, double %b) nounwind {
; RV32IZFINXZDINX-LABEL: fmv_x_d:
; RV32IZFINXZDINX: # %bb.0:
; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 4(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 4(sp)
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a2
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
@@ -1353,21 +1276,17 @@ define double @fmv_d_x(i64 %a, i64 %b) nounwind {
;
; RV32IZFINXZDINX-LABEL: fmv_d_x:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -32
-; RV32IZFINXZDINX-NEXT: sw a3, 20(sp)
-; RV32IZFINXZDINX-NEXT: sw a2, 16(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 28(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 24(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 16(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 20(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 24(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 28(sp)
-; RV32IZFINXZDINX-NEXT: fadd.d a0, a2, a0
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
+; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
+; RV32IZFINXZDINX-NEXT: sw a3, 4(sp)
+; RV32IZFINXZDINX-NEXT: sw a2, 0(sp)
; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 32
+; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
+; RV32IZFINXZDINX-NEXT: lw a0, 0(sp)
+; RV32IZFINXZDINX-NEXT: lw a1, 4(sp)
+; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
+; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
+; RV32IZFINXZDINX-NEXT: fadd.d a0, a2, a0
+; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fmv_d_x:
@@ -1406,13 +1325,7 @@ define double @fcvt_d_w_i8(i8 signext %a) nounwind {
;
; RV32IZFINXZDINX-LABEL: fcvt_d_w_i8:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
; RV32IZFINXZDINX-NEXT: fcvt.d.w a0, a0
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_d_w_i8:
@@ -1449,13 +1362,7 @@ define double @fcvt_d_wu_i8(i8 zeroext %a) nounwind {
;
; RV32IZFINXZDINX-LABEL: fcvt_d_wu_i8:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
; RV32IZFINXZDINX-NEXT: fcvt.d.wu a0, a0
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_d_wu_i8:
@@ -1492,13 +1399,7 @@ define double @fcvt_d_w_i16(i16 signext %a) nounwind {
;
; RV32IZFINXZDINX-LABEL: fcvt_d_w_i16:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
; RV32IZFINXZDINX-NEXT: fcvt.d.w a0, a0
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_d_w_i16:
@@ -1535,13 +1436,7 @@ define double @fcvt_d_wu_i16(i16 zeroext %a) nounwind {
;
; RV32IZFINXZDINX-LABEL: fcvt_d_wu_i16:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
; RV32IZFINXZDINX-NEXT: fcvt.d.wu a0, a0
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_d_wu_i16:
@@ -1731,13 +1626,7 @@ define signext i16 @fcvt_w_s_i16(double %a) nounwind {
;
; RV32IZFINXZDINX-LABEL: fcvt_w_s_i16:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rtz
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_w_s_i16:
@@ -1797,24 +1686,18 @@ define signext i16 @fcvt_w_s_sat_i16(double %a) nounwind {
;
; RV32IZFINXZDINX-LABEL: fcvt_w_s_sat_i16:
; RV32IZFINXZDINX: # %bb.0: # %start
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI26_0)
; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI26_0+4)(a2)
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI26_0)(a2)
; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI26_1)
; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI26_1+4)(a4)
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI26_1)(a4)
-; RV32IZFINXZDINX-NEXT: fmax.d a2, a0, a2
-; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a0
-; RV32IZFINXZDINX-NEXT: neg a0, a0
-; RV32IZFINXZDINX-NEXT: fmin.d a2, a2, a4
-; RV32IZFINXZDINX-NEXT: fcvt.w.d a1, a2, rtz
-; RV32IZFINXZDINX-NEXT: and a0, a0, a1
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
+; RV32IZFINXZDINX-NEXT: feq.d a6, a0, a0
+; RV32IZFINXZDINX-NEXT: neg a6, a6
+; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a2
+; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a4
+; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rtz
+; RV32IZFINXZDINX-NEXT: and a0, a6, a0
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_w_s_sat_i16:
@@ -1948,13 +1831,7 @@ define zeroext i16 @fcvt_wu_s_i16(double %a) nounwind {
;
; RV32IZFINXZDINX-LABEL: fcvt_wu_s_i16:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_wu_s_i16:
@@ -2006,11 +1883,6 @@ define zeroext i16 @fcvt_wu_s_sat_i16(double %a) nounwind {
;
; RV32IZFINXZDINX-LABEL: fcvt_wu_s_sat_i16:
; RV32IZFINXZDINX: # %bb.0: # %start
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI28_0)
; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI28_0+4)(a2)
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI28_0)(a2)
@@ -2018,7 +1890,6 @@ define zeroext i16 @fcvt_wu_s_sat_i16(double %a) nounwind {
; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a4
; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a2
; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_wu_s_sat_i16:
@@ -2130,13 +2001,7 @@ define signext i8 @fcvt_w_s_i8(double %a) nounwind {
;
; RV32IZFINXZDINX-LABEL: fcvt_w_s_i8:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rtz
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_w_s_i8:
@@ -2196,24 +2061,18 @@ define signext i8 @fcvt_w_s_sat_i8(double %a) nounwind {
;
; RV32IZFINXZDINX-LABEL: fcvt_w_s_sat_i8:
; RV32IZFINXZDINX: # %bb.0: # %start
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI30_0)
; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI30_0+4)(a2)
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI30_0)(a2)
; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI30_1)
; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI30_1+4)(a4)
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI30_1)(a4)
-; RV32IZFINXZDINX-NEXT: fmax.d a2, a0, a2
-; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a0
-; RV32IZFINXZDINX-NEXT: neg a0, a0
-; RV32IZFINXZDINX-NEXT: fmin.d a2, a2, a4
-; RV32IZFINXZDINX-NEXT: fcvt.w.d a1, a2, rtz
-; RV32IZFINXZDINX-NEXT: and a0, a0, a1
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
+; RV32IZFINXZDINX-NEXT: feq.d a6, a0, a0
+; RV32IZFINXZDINX-NEXT: neg a6, a6
+; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a2
+; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a4
+; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rtz
+; RV32IZFINXZDINX-NEXT: and a0, a6, a0
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_w_s_sat_i8:
@@ -2344,13 +2203,7 @@ define zeroext i8 @fcvt_wu_s_i8(double %a) nounwind {
;
; RV32IZFINXZDINX-LABEL: fcvt_wu_s_i8:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_wu_s_i8:
@@ -2404,11 +2257,6 @@ define zeroext i8 @fcvt_wu_s_sat_i8(double %a) nounwind {
;
; RV32IZFINXZDINX-LABEL: fcvt_wu_s_sat_i8:
; RV32IZFINXZDINX: # %bb.0: # %start
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI32_0)
; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI32_0+4)(a2)
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI32_0)(a2)
@@ -2416,7 +2264,6 @@ define zeroext i8 @fcvt_wu_s_sat_i8(double %a) nounwind {
; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a4
; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a2
; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_wu_s_sat_i8:
@@ -2532,17 +2379,11 @@ define zeroext i32 @fcvt_wu_d_sat_zext(double %a) nounwind {
;
; RV32IZFINXZDINX-LABEL: fcvt_wu_d_sat_zext:
; RV32IZFINXZDINX: # %bb.0: # %start
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.wu.d a2, a0, rtz
; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a0
; RV32IZFINXZDINX-NEXT: seqz a0, a0
; RV32IZFINXZDINX-NEXT: addi a0, a0, -1
; RV32IZFINXZDINX-NEXT: and a0, a0, a2
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_wu_d_sat_zext:
@@ -2647,17 +2488,11 @@ define signext i32 @fcvt_w_d_sat_sext(double %a) nounwind {
;
; RV32IZFINXZDINX-LABEL: fcvt_w_d_sat_sext:
; RV32IZFINXZDINX: # %bb.0: # %start
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.w.d a2, a0, rtz
; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a0
; RV32IZFINXZDINX-NEXT: seqz a0, a0
; RV32IZFINXZDINX-NEXT: addi a0, a0, -1
; RV32IZFINXZDINX-NEXT: and a0, a0, a2
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_w_d_sat_sext:
diff --git a/llvm/test/CodeGen/RISCV/double-fcmp-strict.ll b/llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
index 3ae2e997019caa..e864d8fb0eddd5 100644
--- a/llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
+++ b/llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
@@ -24,17 +24,7 @@ define i32 @fcmp_oeq(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmp_oeq:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a2
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcmp_oeq:
@@ -78,20 +68,11 @@ define i32 @fcmp_ogt(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmp_ogt:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: csrr a1, fflags
-; RV32IZFINXZDINX-NEXT: flt.d a0, a2, a4
-; RV32IZFINXZDINX-NEXT: csrw fflags, a1
-; RV32IZFINXZDINX-NEXT: feq.d zero, a2, a4
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
+; RV32IZFINXZDINX-NEXT: csrr a5, fflags
+; RV32IZFINXZDINX-NEXT: flt.d a4, a2, a0
+; RV32IZFINXZDINX-NEXT: csrw fflags, a5
+; RV32IZFINXZDINX-NEXT: feq.d zero, a2, a0
+; RV32IZFINXZDINX-NEXT: mv a0, a4
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcmp_ogt:
@@ -138,20 +119,11 @@ define i32 @fcmp_oge(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmp_oge:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: csrr a1, fflags
-; RV32IZFINXZDINX-NEXT: fle.d a0, a2, a4
-; RV32IZFINXZDINX-NEXT: csrw fflags, a1
-; RV32IZFINXZDINX-NEXT: feq.d zero, a2, a4
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
+; RV32IZFINXZDINX-NEXT: csrr a5, fflags
+; RV32IZFINXZDINX-NEXT: fle.d a4, a2, a0
+; RV32IZFINXZDINX-NEXT: csrw fflags, a5
+; RV32IZFINXZDINX-NEXT: feq.d zero, a2, a0
+; RV32IZFINXZDINX-NEXT: mv a0, a4
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcmp_oge:
@@ -200,20 +172,11 @@ define i32 @fcmp_olt(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmp_olt:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: csrr a1, fflags
-; RV32IZFINXZDINX-NEXT: flt.d a0, a4, a2
-; RV32IZFINXZDINX-NEXT: csrw fflags, a1
-; RV32IZFINXZDINX-NEXT: feq.d zero, a4, a2
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
+; RV32IZFINXZDINX-NEXT: csrr a5, fflags
+; RV32IZFINXZDINX-NEXT: flt.d a4, a0, a2
+; RV32IZFINXZDINX-NEXT: csrw fflags, a5
+; RV32IZFINXZDINX-NEXT: feq.d zero, a0, a2
+; RV32IZFINXZDINX-NEXT: mv a0, a4
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcmp_olt:
@@ -260,20 +223,11 @@ define i32 @fcmp_ole(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmp_ole:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: csrr a1, fflags
-; RV32IZFINXZDINX-NEXT: fle.d a0, a4, a2
-; RV32IZFINXZDINX-NEXT: csrw fflags, a1
-; RV32IZFINXZDINX-NEXT: feq.d zero, a4, a2
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
+; RV32IZFINXZDINX-NEXT: csrr a5, fflags
+; RV32IZFINXZDINX-NEXT: fle.d a4, a0, a2
+; RV32IZFINXZDINX-NEXT: csrw fflags, a5
+; RV32IZFINXZDINX-NEXT: feq.d zero, a0, a2
+; RV32IZFINXZDINX-NEXT: mv a0, a4
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcmp_ole:
@@ -327,25 +281,16 @@ define i32 @fcmp_one(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmp_one:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: csrr a0, fflags
-; RV32IZFINXZDINX-NEXT: flt.d a1, a4, a2
-; RV32IZFINXZDINX-NEXT: csrw fflags, a0
-; RV32IZFINXZDINX-NEXT: feq.d zero, a4, a2
-; RV32IZFINXZDINX-NEXT: csrr a0, fflags
-; RV32IZFINXZDINX-NEXT: flt.d a6, a2, a4
-; RV32IZFINXZDINX-NEXT: csrw fflags, a0
-; RV32IZFINXZDINX-NEXT: or a0, a6, a1
-; RV32IZFINXZDINX-NEXT: feq.d zero, a2, a4
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
+; RV32IZFINXZDINX-NEXT: csrr a4, fflags
+; RV32IZFINXZDINX-NEXT: flt.d a5, a0, a2
+; RV32IZFINXZDINX-NEXT: csrw fflags, a4
+; RV32IZFINXZDINX-NEXT: feq.d zero, a0, a2
+; RV32IZFINXZDINX-NEXT: csrr a4, fflags
+; RV32IZFINXZDINX-NEXT: flt.d a6, a2, a0
+; RV32IZFINXZDINX-NEXT: csrw fflags, a4
+; RV32IZFINXZDINX-NEXT: or a4, a6, a5
+; RV32IZFINXZDINX-NEXT: feq.d zero, a2, a0
+; RV32IZFINXZDINX-NEXT: mv a0, a4
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcmp_one:
@@ -430,19 +375,9 @@ define i32 @fcmp_ord(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmp_ord:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
; RV32IZFINXZDINX-NEXT: feq.d a2, a2, a2
; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a0
; RV32IZFINXZDINX-NEXT: and a0, a0, a2
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcmp_ord:
@@ -495,26 +430,17 @@ define i32 @fcmp_ueq(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmp_ueq:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: csrr a0, fflags
-; RV32IZFINXZDINX-NEXT: flt.d a1, a4, a2
-; RV32IZFINXZDINX-NEXT: csrw fflags, a0
-; RV32IZFINXZDINX-NEXT: feq.d zero, a4, a2
-; RV32IZFINXZDINX-NEXT: csrr a0, fflags
-; RV32IZFINXZDINX-NEXT: flt.d a6, a2, a4
-; RV32IZFINXZDINX-NEXT: csrw fflags, a0
-; RV32IZFINXZDINX-NEXT: or a0, a6, a1
-; RV32IZFINXZDINX-NEXT: xori a0, a0, 1
-; RV32IZFINXZDINX-NEXT: feq.d zero, a2, a4
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
+; RV32IZFINXZDINX-NEXT: csrr a4, fflags
+; RV32IZFINXZDINX-NEXT: flt.d a5, a0, a2
+; RV32IZFINXZDINX-NEXT: csrw fflags, a4
+; RV32IZFINXZDINX-NEXT: feq.d zero, a0, a2
+; RV32IZFINXZDINX-NEXT: csrr a4, fflags
+; RV32IZFINXZDINX-NEXT: flt.d a6, a2, a0
+; RV32IZFINXZDINX-NEXT: csrw fflags, a4
+; RV32IZFINXZDINX-NEXT: or a4, a6, a5
+; RV32IZFINXZDINX-NEXT: xori a4, a4, 1
+; RV32IZFINXZDINX-NEXT: feq.d zero, a2, a0
+; RV32IZFINXZDINX-NEXT: mv a0, a4
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcmp_ueq:
@@ -602,21 +528,12 @@ define i32 @fcmp_ugt(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmp_ugt:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: csrr a0, fflags
-; RV32IZFINXZDINX-NEXT: fle.d a1, a4, a2
-; RV32IZFINXZDINX-NEXT: csrw fflags, a0
-; RV32IZFINXZDINX-NEXT: xori a0, a1, 1
-; RV32IZFINXZDINX-NEXT: feq.d zero, a4, a2
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
+; RV32IZFINXZDINX-NEXT: csrr a4, fflags
+; RV32IZFINXZDINX-NEXT: fle.d a5, a0, a2
+; RV32IZFINXZDINX-NEXT: csrw fflags, a4
+; RV32IZFINXZDINX-NEXT: xori a4, a5, 1
+; RV32IZFINXZDINX-NEXT: feq.d zero, a0, a2
+; RV32IZFINXZDINX-NEXT: mv a0, a4
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcmp_ugt:
@@ -665,21 +582,12 @@ define i32 @fcmp_uge(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmp_uge:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: csrr a0, fflags
-; RV32IZFINXZDINX-NEXT: flt.d a1, a4, a2
-; RV32IZFINXZDINX-NEXT: csrw fflags, a0
-; RV32IZFINXZDINX-NEXT: xori a0, a1, 1
-; RV32IZFINXZDINX-NEXT: feq.d zero, a4, a2
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
+; RV32IZFINXZDINX-NEXT: csrr a4, fflags
+; RV32IZFINXZDINX-NEXT: flt.d a5, a0, a2
+; RV32IZFINXZDINX-NEXT: csrw fflags, a4
+; RV32IZFINXZDINX-NEXT: xori a4, a5, 1
+; RV32IZFINXZDINX-NEXT: feq.d zero, a0, a2
+; RV32IZFINXZDINX-NEXT: mv a0, a4
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcmp_uge:
@@ -730,21 +638,12 @@ define i32 @fcmp_ult(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmp_ult:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: csrr a0, fflags
-; RV32IZFINXZDINX-NEXT: fle.d a1, a2, a4
-; RV32IZFINXZDINX-NEXT: csrw fflags, a0
-; RV32IZFINXZDINX-NEXT: xori a0, a1, 1
-; RV32IZFINXZDINX-NEXT: feq.d zero, a2, a4
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
+; RV32IZFINXZDINX-NEXT: csrr a4, fflags
+; RV32IZFINXZDINX-NEXT: fle.d a5, a2, a0
+; RV32IZFINXZDINX-NEXT: csrw fflags, a4
+; RV32IZFINXZDINX-NEXT: xori a4, a5, 1
+; RV32IZFINXZDINX-NEXT: feq.d zero, a2, a0
+; RV32IZFINXZDINX-NEXT: mv a0, a4
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcmp_ult:
@@ -793,21 +692,12 @@ define i32 @fcmp_ule(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmp_ule:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: csrr a0, fflags
-; RV32IZFINXZDINX-NEXT: flt.d a1, a2, a4
-; RV32IZFINXZDINX-NEXT: csrw fflags, a0
-; RV32IZFINXZDINX-NEXT: xori a0, a1, 1
-; RV32IZFINXZDINX-NEXT: feq.d zero, a2, a4
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
+; RV32IZFINXZDINX-NEXT: csrr a4, fflags
+; RV32IZFINXZDINX-NEXT: flt.d a5, a2, a0
+; RV32IZFINXZDINX-NEXT: csrw fflags, a4
+; RV32IZFINXZDINX-NEXT: xori a4, a5, 1
+; RV32IZFINXZDINX-NEXT: feq.d zero, a2, a0
+; RV32IZFINXZDINX-NEXT: mv a0, a4
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcmp_ule:
@@ -853,18 +743,8 @@ define i32 @fcmp_une(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmp_une:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a2
; RV32IZFINXZDINX-NEXT: xori a0, a0, 1
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcmp_une:
@@ -908,20 +788,10 @@ define i32 @fcmp_uno(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmp_uno:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
; RV32IZFINXZDINX-NEXT: feq.d a2, a2, a2
; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a0
; RV32IZFINXZDINX-NEXT: and a0, a0, a2
; RV32IZFINXZDINX-NEXT: xori a0, a0, 1
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcmp_uno:
@@ -966,19 +836,9 @@ define i32 @fcmps_oeq(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmps_oeq:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
; RV32IZFINXZDINX-NEXT: fle.d a4, a2, a0
; RV32IZFINXZDINX-NEXT: fle.d a0, a0, a2
; RV32IZFINXZDINX-NEXT: and a0, a0, a4
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcmps_oeq:
@@ -1021,17 +881,7 @@ define i32 @fcmps_ogt(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmps_ogt:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
; RV32IZFINXZDINX-NEXT: flt.d a0, a2, a0
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcmps_ogt:
@@ -1071,17 +921,7 @@ define i32 @fcmps_oge(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmps_oge:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
; RV32IZFINXZDINX-NEXT: fle.d a0, a2, a0
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcmps_oge:
@@ -1123,17 +963,7 @@ define i32 @fcmps_olt(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmps_olt:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: flt.d a0, a0, a2
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcmps_olt:
@@ -1173,17 +1003,7 @@ define i32 @fcmps_ole(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmps_ole:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fle.d a0, a0, a2
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcmps_ole:
@@ -1225,19 +1045,9 @@ define i32 @fcmps_one(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmps_one:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: flt.d a4, a0, a2
; RV32IZFINXZDINX-NEXT: flt.d a0, a2, a0
; RV32IZFINXZDINX-NEXT: or a0, a0, a4
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcmps_one:
@@ -1315,19 +1125,9 @@ define i32 @fcmps_ord(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmps_ord:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
; RV32IZFINXZDINX-NEXT: fle.d a2, a2, a2
; RV32IZFINXZDINX-NEXT: fle.d a0, a0, a0
; RV32IZFINXZDINX-NEXT: and a0, a0, a2
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcmps_ord:
@@ -1372,20 +1172,10 @@ define i32 @fcmps_ueq(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmps_ueq:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: flt.d a4, a0, a2
; RV32IZFINXZDINX-NEXT: flt.d a0, a2, a0
; RV32IZFINXZDINX-NEXT: or a0, a0, a4
; RV32IZFINXZDINX-NEXT: xori a0, a0, 1
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcmps_ueq:
@@ -1463,18 +1253,8 @@ define i32 @fcmps_ugt(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmps_ugt:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fle.d a0, a0, a2
; RV32IZFINXZDINX-NEXT: xori a0, a0, 1
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcmps_ugt:
@@ -1516,18 +1296,8 @@ define i32 @fcmps_uge(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmps_uge:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: flt.d a0, a0, a2
; RV32IZFINXZDINX-NEXT: xori a0, a0, 1
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcmps_uge:
@@ -1571,18 +1341,8 @@ define i32 @fcmps_ult(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmps_ult:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
; RV32IZFINXZDINX-NEXT: fle.d a0, a2, a0
; RV32IZFINXZDINX-NEXT: xori a0, a0, 1
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcmps_ult:
@@ -1624,18 +1384,8 @@ define i32 @fcmps_ule(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmps_ule:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
; RV32IZFINXZDINX-NEXT: flt.d a0, a2, a0
; RV32IZFINXZDINX-NEXT: xori a0, a0, 1
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcmps_ule:
@@ -1679,20 +1429,10 @@ define i32 @fcmps_une(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmps_une:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
; RV32IZFINXZDINX-NEXT: fle.d a4, a2, a0
; RV32IZFINXZDINX-NEXT: fle.d a0, a0, a2
; RV32IZFINXZDINX-NEXT: and a0, a0, a4
; RV32IZFINXZDINX-NEXT: xori a0, a0, 1
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcmps_une:
@@ -1738,20 +1478,10 @@ define i32 @fcmps_uno(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmps_uno:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
; RV32IZFINXZDINX-NEXT: fle.d a2, a2, a2
; RV32IZFINXZDINX-NEXT: fle.d a0, a0, a0
; RV32IZFINXZDINX-NEXT: and a0, a0, a2
; RV32IZFINXZDINX-NEXT: xori a0, a0, 1
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcmps_uno:
diff --git a/llvm/test/CodeGen/RISCV/double-fcmp.ll b/llvm/test/CodeGen/RISCV/double-fcmp.ll
index 64a154f450f183..1e609f8081ebfb 100644
--- a/llvm/test/CodeGen/RISCV/double-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/double-fcmp.ll
@@ -45,17 +45,7 @@ define i32 @fcmp_oeq(double %a, double %b) nounwind {
;
; CHECKRV32IZFINXZDINX-LABEL: fcmp_oeq:
; CHECKRV32IZFINXZDINX: # %bb.0:
-; CHECKRV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; CHECKRV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; CHECKRV32IZFINXZDINX-NEXT: feq.d a0, a0, a2
-; CHECKRV32IZFINXZDINX-NEXT: addi sp, sp, 16
; CHECKRV32IZFINXZDINX-NEXT: ret
;
; CHECKRV64IZFINXZDINX-LABEL: fcmp_oeq:
@@ -95,17 +85,7 @@ define i32 @fcmp_ogt(double %a, double %b) nounwind {
;
; CHECKRV32IZFINXZDINX-LABEL: fcmp_ogt:
; CHECKRV32IZFINXZDINX: # %bb.0:
-; CHECKRV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; CHECKRV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a3, 12(sp)
; CHECKRV32IZFINXZDINX-NEXT: flt.d a0, a2, a0
-; CHECKRV32IZFINXZDINX-NEXT: addi sp, sp, 16
; CHECKRV32IZFINXZDINX-NEXT: ret
;
; CHECKRV64IZFINXZDINX-LABEL: fcmp_ogt:
@@ -145,17 +125,7 @@ define i32 @fcmp_oge(double %a, double %b) nounwind {
;
; CHECKRV32IZFINXZDINX-LABEL: fcmp_oge:
; CHECKRV32IZFINXZDINX: # %bb.0:
-; CHECKRV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; CHECKRV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a3, 12(sp)
; CHECKRV32IZFINXZDINX-NEXT: fle.d a0, a2, a0
-; CHECKRV32IZFINXZDINX-NEXT: addi sp, sp, 16
; CHECKRV32IZFINXZDINX-NEXT: ret
;
; CHECKRV64IZFINXZDINX-LABEL: fcmp_oge:
@@ -197,17 +167,7 @@ define i32 @fcmp_olt(double %a, double %b) nounwind {
;
; CHECKRV32IZFINXZDINX-LABEL: fcmp_olt:
; CHECKRV32IZFINXZDINX: # %bb.0:
-; CHECKRV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; CHECKRV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; CHECKRV32IZFINXZDINX-NEXT: flt.d a0, a0, a2
-; CHECKRV32IZFINXZDINX-NEXT: addi sp, sp, 16
; CHECKRV32IZFINXZDINX-NEXT: ret
;
; CHECKRV64IZFINXZDINX-LABEL: fcmp_olt:
@@ -247,17 +207,7 @@ define i32 @fcmp_ole(double %a, double %b) nounwind {
;
; CHECKRV32IZFINXZDINX-LABEL: fcmp_ole:
; CHECKRV32IZFINXZDINX: # %bb.0:
-; CHECKRV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; CHECKRV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; CHECKRV32IZFINXZDINX-NEXT: fle.d a0, a0, a2
-; CHECKRV32IZFINXZDINX-NEXT: addi sp, sp, 16
; CHECKRV32IZFINXZDINX-NEXT: ret
;
; CHECKRV64IZFINXZDINX-LABEL: fcmp_ole:
@@ -299,19 +249,9 @@ define i32 @fcmp_one(double %a, double %b) nounwind {
;
; CHECKRV32IZFINXZDINX-LABEL: fcmp_one:
; CHECKRV32IZFINXZDINX: # %bb.0:
-; CHECKRV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; CHECKRV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; CHECKRV32IZFINXZDINX-NEXT: flt.d a4, a0, a2
; CHECKRV32IZFINXZDINX-NEXT: flt.d a0, a2, a0
; CHECKRV32IZFINXZDINX-NEXT: or a0, a0, a4
-; CHECKRV32IZFINXZDINX-NEXT: addi sp, sp, 16
; CHECKRV32IZFINXZDINX-NEXT: ret
;
; CHECKRV64IZFINXZDINX-LABEL: fcmp_one:
@@ -389,19 +329,9 @@ define i32 @fcmp_ord(double %a, double %b) nounwind {
;
; CHECKRV32IZFINXZDINX-LABEL: fcmp_ord:
; CHECKRV32IZFINXZDINX: # %bb.0:
-; CHECKRV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; CHECKRV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a3, 12(sp)
; CHECKRV32IZFINXZDINX-NEXT: feq.d a2, a2, a2
; CHECKRV32IZFINXZDINX-NEXT: feq.d a0, a0, a0
; CHECKRV32IZFINXZDINX-NEXT: and a0, a0, a2
-; CHECKRV32IZFINXZDINX-NEXT: addi sp, sp, 16
; CHECKRV32IZFINXZDINX-NEXT: ret
;
; CHECKRV64IZFINXZDINX-LABEL: fcmp_ord:
@@ -446,20 +376,10 @@ define i32 @fcmp_ueq(double %a, double %b) nounwind {
;
; CHECKRV32IZFINXZDINX-LABEL: fcmp_ueq:
; CHECKRV32IZFINXZDINX: # %bb.0:
-; CHECKRV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; CHECKRV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; CHECKRV32IZFINXZDINX-NEXT: flt.d a4, a0, a2
; CHECKRV32IZFINXZDINX-NEXT: flt.d a0, a2, a0
; CHECKRV32IZFINXZDINX-NEXT: or a0, a0, a4
; CHECKRV32IZFINXZDINX-NEXT: xori a0, a0, 1
-; CHECKRV32IZFINXZDINX-NEXT: addi sp, sp, 16
; CHECKRV32IZFINXZDINX-NEXT: ret
;
; CHECKRV64IZFINXZDINX-LABEL: fcmp_ueq:
@@ -537,18 +457,8 @@ define i32 @fcmp_ugt(double %a, double %b) nounwind {
;
; CHECKRV32IZFINXZDINX-LABEL: fcmp_ugt:
; CHECKRV32IZFINXZDINX: # %bb.0:
-; CHECKRV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; CHECKRV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; CHECKRV32IZFINXZDINX-NEXT: fle.d a0, a0, a2
; CHECKRV32IZFINXZDINX-NEXT: xori a0, a0, 1
-; CHECKRV32IZFINXZDINX-NEXT: addi sp, sp, 16
; CHECKRV32IZFINXZDINX-NEXT: ret
;
; CHECKRV64IZFINXZDINX-LABEL: fcmp_ugt:
@@ -590,18 +500,8 @@ define i32 @fcmp_uge(double %a, double %b) nounwind {
;
; CHECKRV32IZFINXZDINX-LABEL: fcmp_uge:
; CHECKRV32IZFINXZDINX: # %bb.0:
-; CHECKRV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; CHECKRV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; CHECKRV32IZFINXZDINX-NEXT: flt.d a0, a0, a2
; CHECKRV32IZFINXZDINX-NEXT: xori a0, a0, 1
-; CHECKRV32IZFINXZDINX-NEXT: addi sp, sp, 16
; CHECKRV32IZFINXZDINX-NEXT: ret
;
; CHECKRV64IZFINXZDINX-LABEL: fcmp_uge:
@@ -645,18 +545,8 @@ define i32 @fcmp_ult(double %a, double %b) nounwind {
;
; CHECKRV32IZFINXZDINX-LABEL: fcmp_ult:
; CHECKRV32IZFINXZDINX: # %bb.0:
-; CHECKRV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; CHECKRV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a3, 12(sp)
; CHECKRV32IZFINXZDINX-NEXT: fle.d a0, a2, a0
; CHECKRV32IZFINXZDINX-NEXT: xori a0, a0, 1
-; CHECKRV32IZFINXZDINX-NEXT: addi sp, sp, 16
; CHECKRV32IZFINXZDINX-NEXT: ret
;
; CHECKRV64IZFINXZDINX-LABEL: fcmp_ult:
@@ -698,18 +588,8 @@ define i32 @fcmp_ule(double %a, double %b) nounwind {
;
; CHECKRV32IZFINXZDINX-LABEL: fcmp_ule:
; CHECKRV32IZFINXZDINX: # %bb.0:
-; CHECKRV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; CHECKRV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a3, 12(sp)
; CHECKRV32IZFINXZDINX-NEXT: flt.d a0, a2, a0
; CHECKRV32IZFINXZDINX-NEXT: xori a0, a0, 1
-; CHECKRV32IZFINXZDINX-NEXT: addi sp, sp, 16
; CHECKRV32IZFINXZDINX-NEXT: ret
;
; CHECKRV64IZFINXZDINX-LABEL: fcmp_ule:
@@ -751,18 +631,8 @@ define i32 @fcmp_une(double %a, double %b) nounwind {
;
; CHECKRV32IZFINXZDINX-LABEL: fcmp_une:
; CHECKRV32IZFINXZDINX: # %bb.0:
-; CHECKRV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; CHECKRV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; CHECKRV32IZFINXZDINX-NEXT: feq.d a0, a0, a2
; CHECKRV32IZFINXZDINX-NEXT: xori a0, a0, 1
-; CHECKRV32IZFINXZDINX-NEXT: addi sp, sp, 16
; CHECKRV32IZFINXZDINX-NEXT: ret
;
; CHECKRV64IZFINXZDINX-LABEL: fcmp_une:
@@ -806,20 +676,10 @@ define i32 @fcmp_uno(double %a, double %b) nounwind {
;
; CHECKRV32IZFINXZDINX-LABEL: fcmp_uno:
; CHECKRV32IZFINXZDINX: # %bb.0:
-; CHECKRV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; CHECKRV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT: lw a3, 12(sp)
; CHECKRV32IZFINXZDINX-NEXT: feq.d a2, a2, a2
; CHECKRV32IZFINXZDINX-NEXT: feq.d a0, a0, a0
; CHECKRV32IZFINXZDINX-NEXT: and a0, a0, a2
; CHECKRV32IZFINXZDINX-NEXT: xori a0, a0, 1
-; CHECKRV32IZFINXZDINX-NEXT: addi sp, sp, 16
; CHECKRV32IZFINXZDINX-NEXT: ret
;
; CHECKRV64IZFINXZDINX-LABEL: fcmp_uno:
diff --git a/llvm/test/CodeGen/RISCV/double-imm.ll b/llvm/test/CodeGen/RISCV/double-imm.ll
index 9254369baf19f3..74d4acc4f23f8c 100644
--- a/llvm/test/CodeGen/RISCV/double-imm.ll
+++ b/llvm/test/CodeGen/RISCV/double-imm.ll
@@ -54,20 +54,10 @@ define double @double_imm_op(double %a) nounwind {
;
; CHECKRV32ZDINX-LABEL: double_imm_op:
; CHECKRV32ZDINX: # %bb.0:
-; CHECKRV32ZDINX-NEXT: addi sp, sp, -16
-; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a1, 12(sp)
; CHECKRV32ZDINX-NEXT: lui a2, %hi(.LCPI1_0)
; CHECKRV32ZDINX-NEXT: lw a3, %lo(.LCPI1_0+4)(a2)
; CHECKRV32ZDINX-NEXT: lw a2, %lo(.LCPI1_0)(a2)
; CHECKRV32ZDINX-NEXT: fadd.d a0, a0, a2
-; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: addi sp, sp, 16
; CHECKRV32ZDINX-NEXT: ret
;
; CHECKRV64ZDINX-LABEL: double_imm_op:
@@ -153,24 +143,18 @@ define dso_local double @negzero_sel(i16 noundef %a, double noundef %d) nounwind
;
; CHECKRV32ZDINX-LABEL: negzero_sel:
; CHECKRV32ZDINX: # %bb.0: # %entry
-; CHECKRV32ZDINX-NEXT: addi sp, sp, -16
-; CHECKRV32ZDINX-NEXT: sw a1, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a2, 12(sp)
-; CHECKRV32ZDINX-NEXT: slli a2, a0, 16
-; CHECKRV32ZDINX-NEXT: fcvt.d.w a0, zero
-; CHECKRV32ZDINX-NEXT: beqz a2, .LBB4_2
+; CHECKRV32ZDINX-NEXT: slli a0, a0, 16
+; CHECKRV32ZDINX-NEXT: fcvt.d.w a4, zero
+; CHECKRV32ZDINX-NEXT: beqz a0, .LBB4_2
; CHECKRV32ZDINX-NEXT: # %bb.1: # %entry
-; CHECKRV32ZDINX-NEXT: fneg.d a0, a0
+; CHECKRV32ZDINX-NEXT: fneg.d a2, a4
; CHECKRV32ZDINX-NEXT: j .LBB4_3
; CHECKRV32ZDINX-NEXT: .LBB4_2:
-; CHECKRV32ZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a1, 12(sp)
+; CHECKRV32ZDINX-NEXT: mv a3, a2
+; CHECKRV32ZDINX-NEXT: mv a2, a1
; CHECKRV32ZDINX-NEXT: .LBB4_3: # %entry
-; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: addi sp, sp, 16
+; CHECKRV32ZDINX-NEXT: mv a0, a2
+; CHECKRV32ZDINX-NEXT: mv a1, a3
; CHECKRV32ZDINX-NEXT: ret
;
; CHECKRV64ZDINX-LABEL: negzero_sel:
diff --git a/llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll b/llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll
index c574f64150a249..38215860193eaf 100644
--- a/llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll
+++ b/llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll
@@ -28,17 +28,7 @@ define double @sqrt_f64(double %a) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: sqrt_f64:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fsqrt.d a0, a0
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: sqrt_f64:
@@ -299,22 +289,12 @@ define double @sincos_f64(double %a) nounwind strictfp {
; RV32IZFINXZDINX-NEXT: mv s0, a1
; RV32IZFINXZDINX-NEXT: mv s1, a0
; RV32IZFINXZDINX-NEXT: call sin
-; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw s2, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw s3, 4(sp)
+; RV32IZFINXZDINX-NEXT: mv s2, a0
+; RV32IZFINXZDINX-NEXT: mv s3, a1
; RV32IZFINXZDINX-NEXT: mv a0, s1
; RV32IZFINXZDINX-NEXT: mv a1, s0
; RV32IZFINXZDINX-NEXT: call cos
-; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 4(sp)
; RV32IZFINXZDINX-NEXT: fadd.d a0, s2, a0
-; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 4(sp)
; RV32IZFINXZDINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
@@ -765,25 +745,7 @@ define double @fma_f64(double %a, double %b, double %c) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fma_f64:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fmadd.d a0, a0, a2, a4
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fma_f64:
@@ -822,25 +784,7 @@ define double @fmuladd_f64(double %a, double %b, double %c) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fmuladd_f64:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fmadd.d a0, a0, a2, a4
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fmuladd_f64:
@@ -1455,13 +1399,7 @@ define iXLen @lrint_f64(double %a) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: lrint_f64:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: lrint_f64:
@@ -1505,13 +1443,7 @@ define iXLen @lround_f64(double %a) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: lround_f64:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rmm
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: lround_f64:
diff --git a/llvm/test/CodeGen/RISCV/double-intrinsics.ll b/llvm/test/CodeGen/RISCV/double-intrinsics.ll
index f290cf0f7736e3..52c49cfbfb30a7 100644
--- a/llvm/test/CodeGen/RISCV/double-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/double-intrinsics.ll
@@ -26,17 +26,7 @@ define double @sqrt_f64(double %a) nounwind {
;
; RV32IZFINXZDINX-LABEL: sqrt_f64:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fsqrt.d a0, a0
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: sqrt_f64:
@@ -254,22 +244,12 @@ define double @sincos_f64(double %a) nounwind {
; RV32IZFINXZDINX-NEXT: mv s0, a1
; RV32IZFINXZDINX-NEXT: mv s1, a0
; RV32IZFINXZDINX-NEXT: call sin
-; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw s2, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw s3, 4(sp)
+; RV32IZFINXZDINX-NEXT: mv s2, a0
+; RV32IZFINXZDINX-NEXT: mv s3, a1
; RV32IZFINXZDINX-NEXT: mv a0, s1
; RV32IZFINXZDINX-NEXT: mv a1, s0
; RV32IZFINXZDINX-NEXT: call cos
-; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 4(sp)
; RV32IZFINXZDINX-NEXT: fadd.d a0, s2, a0
-; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 4(sp)
; RV32IZFINXZDINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
@@ -606,25 +586,7 @@ define double @fma_f64(double %a, double %b, double %c) nounwind {
;
; RV32IZFINXZDINX-LABEL: fma_f64:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fmadd.d a0, a0, a2, a4
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fma_f64:
@@ -663,25 +625,7 @@ define double @fmuladd_f64(double %a, double %b, double %c) nounwind {
;
; RV32IZFINXZDINX-LABEL: fmuladd_f64:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fmadd.d a0, a0, a2, a4
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fmuladd_f64:
@@ -769,21 +713,7 @@ define double @minnum_f64(double %a, double %b) nounwind {
;
; RV32IZFINXZDINX-LABEL: minnum_f64:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a2
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: minnum_f64:
@@ -822,21 +752,7 @@ define double @maxnum_f64(double %a, double %b) nounwind {
;
; RV32IZFINXZDINX-LABEL: maxnum_f64:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a2
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: maxnum_f64:
@@ -892,21 +808,7 @@ define double @copysign_f64(double %a, double %b) nounwind {
;
; RV32IZFINXZDINX-LABEL: copysign_f64:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fsgnj.d a0, a0, a2
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: copysign_f64:
@@ -1381,13 +1283,7 @@ define iXLen @lrint_f64(double %a) nounwind {
;
; RV32IZFINXZDINX-LABEL: lrint_f64:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: lrint_f64:
@@ -1432,13 +1328,7 @@ define iXLen @lround_f64(double %a) nounwind {
;
; RV32IZFINXZDINX-LABEL: lround_f64:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rmm
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: lround_f64:
@@ -1475,13 +1365,7 @@ define i32 @lround_i32_f64(double %a) nounwind {
;
; RV32IZFINXZDINX-LABEL: lround_i32_f64:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rmm
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: lround_i32_f64:
@@ -1625,16 +1509,9 @@ define i1 @isnan_d_fpclass(double %x) {
;
; RV32IZFINXZDINX-LABEL: isnan_d_fpclass:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fclass.d a0, a0
; RV32IZFINXZDINX-NEXT: andi a0, a0, 768
; RV32IZFINXZDINX-NEXT: snez a0, a0
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: isnan_d_fpclass:
diff --git a/llvm/test/CodeGen/RISCV/double-isnan.ll b/llvm/test/CodeGen/RISCV/double-isnan.ll
index 4d0b8151f3c43a..6a3779dc2d36d0 100644
--- a/llvm/test/CodeGen/RISCV/double-isnan.ll
+++ b/llvm/test/CodeGen/RISCV/double-isnan.ll
@@ -17,14 +17,8 @@ define zeroext i1 @double_is_nan(double %a) nounwind {
;
; CHECKRV32ZDINX-LABEL: double_is_nan:
; CHECKRV32ZDINX: # %bb.0:
-; CHECKRV32ZDINX-NEXT: addi sp, sp, -16
-; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a1, 12(sp)
; CHECKRV32ZDINX-NEXT: feq.d a0, a0, a0
; CHECKRV32ZDINX-NEXT: xori a0, a0, 1
-; CHECKRV32ZDINX-NEXT: addi sp, sp, 16
; CHECKRV32ZDINX-NEXT: ret
;
; CHECKRV64ZDINX-LABEL: double_is_nan:
@@ -44,13 +38,7 @@ define zeroext i1 @double_not_nan(double %a) nounwind {
;
; CHECKRV32ZDINX-LABEL: double_not_nan:
; CHECKRV32ZDINX: # %bb.0:
-; CHECKRV32ZDINX-NEXT: addi sp, sp, -16
-; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a1, 12(sp)
; CHECKRV32ZDINX-NEXT: feq.d a0, a0, a0
-; CHECKRV32ZDINX-NEXT: addi sp, sp, 16
; CHECKRV32ZDINX-NEXT: ret
;
; CHECKRV64ZDINX-LABEL: double_not_nan:
diff --git a/llvm/test/CodeGen/RISCV/double-maximum-minimum.ll b/llvm/test/CodeGen/RISCV/double-maximum-minimum.ll
index 0ca20783591ada..5229117caa2c29 100644
--- a/llvm/test/CodeGen/RISCV/double-maximum-minimum.ll
+++ b/llvm/test/CodeGen/RISCV/double-maximum-minimum.ll
@@ -36,35 +36,25 @@ define double @fminimum_f64(double %a, double %b) nounwind {
;
; RV32IZFINXZDINX-LABEL: fminimum_f64:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: feq.d a6, a0, a0
; RV32IZFINXZDINX-NEXT: mv a4, a2
; RV32IZFINXZDINX-NEXT: mv a5, a3
-; RV32IZFINXZDINX-NEXT: bnez a6, .LBB0_2
+; RV32IZFINXZDINX-NEXT: beqz a6, .LBB0_3
; RV32IZFINXZDINX-NEXT: # %bb.1:
+; RV32IZFINXZDINX-NEXT: feq.d a6, a2, a2
+; RV32IZFINXZDINX-NEXT: beqz a6, .LBB0_4
+; RV32IZFINXZDINX-NEXT: .LBB0_2:
+; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a4
+; RV32IZFINXZDINX-NEXT: ret
+; RV32IZFINXZDINX-NEXT: .LBB0_3:
; RV32IZFINXZDINX-NEXT: mv a4, a0
; RV32IZFINXZDINX-NEXT: mv a5, a1
-; RV32IZFINXZDINX-NEXT: .LBB0_2:
; RV32IZFINXZDINX-NEXT: feq.d a6, a2, a2
-; RV32IZFINXZDINX-NEXT: bnez a6, .LBB0_4
-; RV32IZFINXZDINX-NEXT: # %bb.3:
+; RV32IZFINXZDINX-NEXT: bnez a6, .LBB0_2
+; RV32IZFINXZDINX-NEXT: .LBB0_4:
; RV32IZFINXZDINX-NEXT: mv a0, a2
; RV32IZFINXZDINX-NEXT: mv a1, a3
-; RV32IZFINXZDINX-NEXT: .LBB0_4:
; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a4
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fminimum_f64:
@@ -113,35 +103,25 @@ define double @fmaximum_f64(double %a, double %b) nounwind {
;
; RV32IZFINXZDINX-LABEL: fmaximum_f64:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: feq.d a6, a0, a0
; RV32IZFINXZDINX-NEXT: mv a4, a2
; RV32IZFINXZDINX-NEXT: mv a5, a3
-; RV32IZFINXZDINX-NEXT: bnez a6, .LBB1_2
+; RV32IZFINXZDINX-NEXT: beqz a6, .LBB1_3
; RV32IZFINXZDINX-NEXT: # %bb.1:
+; RV32IZFINXZDINX-NEXT: feq.d a6, a2, a2
+; RV32IZFINXZDINX-NEXT: beqz a6, .LBB1_4
+; RV32IZFINXZDINX-NEXT: .LBB1_2:
+; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a4
+; RV32IZFINXZDINX-NEXT: ret
+; RV32IZFINXZDINX-NEXT: .LBB1_3:
; RV32IZFINXZDINX-NEXT: mv a4, a0
; RV32IZFINXZDINX-NEXT: mv a5, a1
-; RV32IZFINXZDINX-NEXT: .LBB1_2:
; RV32IZFINXZDINX-NEXT: feq.d a6, a2, a2
-; RV32IZFINXZDINX-NEXT: bnez a6, .LBB1_4
-; RV32IZFINXZDINX-NEXT: # %bb.3:
+; RV32IZFINXZDINX-NEXT: bnez a6, .LBB1_2
+; RV32IZFINXZDINX-NEXT: .LBB1_4:
; RV32IZFINXZDINX-NEXT: mv a0, a2
; RV32IZFINXZDINX-NEXT: mv a1, a3
-; RV32IZFINXZDINX-NEXT: .LBB1_4:
; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a4
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fmaximum_f64:
@@ -174,21 +154,7 @@ define double @fminimum_nnan_f64(double %a, double %b) nounwind {
;
; RV32IZFINXZDINX-LABEL: fminimum_nnan_f64:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a2
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fminimum_nnan_f64:
@@ -221,35 +187,25 @@ define double @fmaximum_nnan_f64(double %a, double %b) nounwind {
;
; RV32IZFINXZDINX-LABEL: fmaximum_nnan_f64:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: feq.d a6, a0, a0
; RV32IZFINXZDINX-NEXT: mv a4, a2
; RV32IZFINXZDINX-NEXT: mv a5, a3
-; RV32IZFINXZDINX-NEXT: bnez a6, .LBB3_2
+; RV32IZFINXZDINX-NEXT: beqz a6, .LBB3_3
; RV32IZFINXZDINX-NEXT: # %bb.1:
+; RV32IZFINXZDINX-NEXT: feq.d a6, a2, a2
+; RV32IZFINXZDINX-NEXT: beqz a6, .LBB3_4
+; RV32IZFINXZDINX-NEXT: .LBB3_2:
+; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a4
+; RV32IZFINXZDINX-NEXT: ret
+; RV32IZFINXZDINX-NEXT: .LBB3_3:
; RV32IZFINXZDINX-NEXT: mv a4, a0
; RV32IZFINXZDINX-NEXT: mv a5, a1
-; RV32IZFINXZDINX-NEXT: .LBB3_2:
; RV32IZFINXZDINX-NEXT: feq.d a6, a2, a2
-; RV32IZFINXZDINX-NEXT: bnez a6, .LBB3_4
-; RV32IZFINXZDINX-NEXT: # %bb.3:
+; RV32IZFINXZDINX-NEXT: bnez a6, .LBB3_2
+; RV32IZFINXZDINX-NEXT: .LBB3_4:
; RV32IZFINXZDINX-NEXT: mv a0, a2
; RV32IZFINXZDINX-NEXT: mv a1, a3
-; RV32IZFINXZDINX-NEXT: .LBB3_4:
; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a4
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fmaximum_nnan_f64:
@@ -289,30 +245,14 @@ define double @fminimum_nnan_op_f64(double %a, double %b) nounwind {
;
; RV32IZFINXZDINX-LABEL: fminimum_nnan_op_f64:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: feq.d a0, a2, a2
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: bnez a0, .LBB4_2
+; RV32IZFINXZDINX-NEXT: feq.d a4, a2, a2
+; RV32IZFINXZDINX-NEXT: bnez a4, .LBB4_2
; RV32IZFINXZDINX-NEXT: # %bb.1:
-; RV32IZFINXZDINX-NEXT: mv a0, a2
-; RV32IZFINXZDINX-NEXT: mv a1, a3
-; RV32IZFINXZDINX-NEXT: j .LBB4_3
+; RV32IZFINXZDINX-NEXT: fmin.d a0, a2, a2
+; RV32IZFINXZDINX-NEXT: ret
; RV32IZFINXZDINX-NEXT: .LBB4_2:
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a0
-; RV32IZFINXZDINX-NEXT: .LBB4_3:
; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a2
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fminimum_nnan_op_f64:
@@ -341,23 +281,9 @@ define double @fmaximum_nnan_op_f64(double %a, double %b) nounwind {
;
; RV32IZFINXZDINX-LABEL: fmaximum_nnan_op_f64:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fadd.d a4, a0, a2
; RV32IZFINXZDINX-NEXT: fsub.d a0, a0, a2
; RV32IZFINXZDINX-NEXT: fmax.d a0, a4, a0
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fmaximum_nnan_op_f64:
diff --git a/llvm/test/CodeGen/RISCV/double-mem.ll b/llvm/test/CodeGen/RISCV/double-mem.ll
index 6c6f70d6e2ed40..38cb52b6f4b302 100644
--- a/llvm/test/CodeGen/RISCV/double-mem.ll
+++ b/llvm/test/CodeGen/RISCV/double-mem.ll
@@ -18,17 +18,11 @@ define dso_local double @fld(ptr %a) nounwind {
;
; RV32IZFINXZDINX-LABEL: fld:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
; RV32IZFINXZDINX-NEXT: lw a2, 0(a0)
; RV32IZFINXZDINX-NEXT: lw a3, 4(a0)
; RV32IZFINXZDINX-NEXT: lw a1, 28(a0)
; RV32IZFINXZDINX-NEXT: lw a0, 24(a0)
; RV32IZFINXZDINX-NEXT: fadd.d a0, a2, a0
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fld:
@@ -56,21 +50,15 @@ define dso_local void @fsd(ptr %a, double %b, double %c) nounwind {
;
; RV32IZFINXZDINX-LABEL: fsd:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a3, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a4, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a4, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a5, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a2, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: fadd.d a2, a2, a4
+; RV32IZFINXZDINX-NEXT: mv a5, a4
+; RV32IZFINXZDINX-NEXT: mv a7, a2
+; RV32IZFINXZDINX-NEXT: mv a4, a3
+; RV32IZFINXZDINX-NEXT: mv a6, a1
+; RV32IZFINXZDINX-NEXT: fadd.d a2, a6, a4
; RV32IZFINXZDINX-NEXT: sw a2, 0(a0)
; RV32IZFINXZDINX-NEXT: sw a3, 4(a0)
; RV32IZFINXZDINX-NEXT: sw a2, 64(a0)
; RV32IZFINXZDINX-NEXT: sw a3, 68(a0)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fsd:
@@ -105,15 +93,6 @@ define dso_local double @fld_fsd_global(double %a, double %b) nounwind {
;
; RV32IZFINXZDINX-LABEL: fld_fsd_global:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a2
; RV32IZFINXZDINX-NEXT: lui a2, %hi(G)
; RV32IZFINXZDINX-NEXT: lw a4, %lo(G)(a2)
@@ -125,11 +104,6 @@ define dso_local double @fld_fsd_global(double %a, double %b) nounwind {
; RV32IZFINXZDINX-NEXT: lw a5, 76(a3)
; RV32IZFINXZDINX-NEXT: sw a0, 72(a3)
; RV32IZFINXZDINX-NEXT: sw a1, 76(a3)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fld_fsd_global:
@@ -174,22 +148,12 @@ define dso_local double @fld_fsd_constant(double %a) nounwind {
;
; RV32IZFINXZDINX-LABEL: fld_fsd_constant:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: lui a2, 912092
; RV32IZFINXZDINX-NEXT: lw a4, -273(a2)
; RV32IZFINXZDINX-NEXT: lw a5, -269(a2)
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a4
; RV32IZFINXZDINX-NEXT: sw a0, -273(a2)
; RV32IZFINXZDINX-NEXT: sw a1, -269(a2)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fld_fsd_constant:
@@ -246,19 +210,13 @@ define dso_local double @fld_stack(double %a) nounwind {
; RV32IZFINXZDINX-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw s0, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw s1, 4(sp)
+; RV32IZFINXZDINX-NEXT: mv s1, a1
+; RV32IZFINXZDINX-NEXT: mv s0, a0
; RV32IZFINXZDINX-NEXT: addi a0, sp, 8
; RV32IZFINXZDINX-NEXT: call notdead
; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, s0
-; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 4(sp)
; RV32IZFINXZDINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
@@ -313,23 +271,15 @@ define dso_local void @fsd_stack(double %a, double %b) nounwind {
;
; RV32IZFINXZDINX-LABEL: fsd_stack:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -32
-; RV32IZFINXZDINX-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
+; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
+; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a2
-; RV32IZFINXZDINX-NEXT: sw a0, 16(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 20(sp)
-; RV32IZFINXZDINX-NEXT: addi a0, sp, 16
+; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)
+; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
+; RV32IZFINXZDINX-NEXT: mv a0, sp
; RV32IZFINXZDINX-NEXT: call notdead
-; RV32IZFINXZDINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 32
+; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fsd_stack:
@@ -360,14 +310,10 @@ define dso_local void @fsd_trunc(ptr %a, double %b) nounwind noinline optnone {
;
; RV32IZFINXZDINX-LABEL: fsd_trunc:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: sw a1, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a2, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
+; RV32IZFINXZDINX-NEXT: mv a3, a2
+; RV32IZFINXZDINX-NEXT: mv a2, a1
; RV32IZFINXZDINX-NEXT: fcvt.s.d a1, a2
; RV32IZFINXZDINX-NEXT: sw a1, 0(a0)
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fsd_trunc:
diff --git a/llvm/test/CodeGen/RISCV/double-previous-failure.ll b/llvm/test/CodeGen/RISCV/double-previous-failure.ll
index 8b8f538886edbd..c169b1099b273a 100644
--- a/llvm/test/CodeGen/RISCV/double-previous-failure.ll
+++ b/llvm/test/CodeGen/RISCV/double-previous-failure.ll
@@ -50,10 +50,6 @@ define i32 @main() nounwind {
; RV32IZFINXZDINX-NEXT: lui a1, 262144
; RV32IZFINXZDINX-NEXT: li a0, 0
; RV32IZFINXZDINX-NEXT: call test
-; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 4(sp)
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI1_0)
; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI1_0+4)(a2)
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI1_0)(a2)
diff --git a/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll b/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
index 7cdf18e2fea9c0..29a9e507095014 100644
--- a/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
+++ b/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
@@ -20,18 +20,11 @@ define signext i32 @test_floor_si32(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_floor_si32:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.w.d a2, a0, rdn
; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a0
; RV32IZFINXZDINX-NEXT: seqz a0, a0
; RV32IZFINXZDINX-NEXT: addi a0, a0, -1
; RV32IZFINXZDINX-NEXT: and a0, a0, a2
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_floor_si32:
@@ -112,13 +105,11 @@ define i64 @test_floor_si64(double %x) nounwind {
; RV32IZFINXZDINX-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: call floor
-; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw s0, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw s1, 4(sp)
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI1_0)
; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI1_0+4)(a2)
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI1_0)(a2)
+; RV32IZFINXZDINX-NEXT: mv s0, a0
+; RV32IZFINXZDINX-NEXT: mv s1, a1
; RV32IZFINXZDINX-NEXT: fle.d s2, a2, s0
; RV32IZFINXZDINX-NEXT: neg s3, s2
; RV32IZFINXZDINX-NEXT: call __fixdfdi
@@ -177,18 +168,11 @@ define signext i32 @test_floor_ui32(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_floor_ui32:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.wu.d a2, a0, rdn
; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a0
; RV32IZFINXZDINX-NEXT: seqz a0, a0
; RV32IZFINXZDINX-NEXT: addi a0, a0, -1
; RV32IZFINXZDINX-NEXT: and a0, a0, a2
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_floor_ui32:
@@ -241,38 +225,30 @@ define i64 @test_floor_ui64(double %x) nounwind {
;
; RV32IZFINXZDINX-LABEL: test_floor_ui64:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -32
-; RV32IZFINXZDINX-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
+; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: call floor
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw s0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw s1, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw s0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw s1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
+; RV32IZFINXZDINX-NEXT: mv s0, a0
+; RV32IZFINXZDINX-NEXT: mv s1, a1
+; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero
+; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI3_0)
+; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI3_0+4)(a4)
+; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI3_0)(a4)
; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
-; RV32IZFINXZDINX-NEXT: neg s2, a2
-; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
-; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI3_0)
-; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI3_0+4)(a2)
-; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI3_0)(a2)
-; RV32IZFINXZDINX-NEXT: and a0, s2, a0
-; RV32IZFINXZDINX-NEXT: flt.d a2, a2, s0
; RV32IZFINXZDINX-NEXT: neg a2, a2
-; RV32IZFINXZDINX-NEXT: or a0, a2, a0
-; RV32IZFINXZDINX-NEXT: and a1, s2, a1
-; RV32IZFINXZDINX-NEXT: or a1, a2, a1
-; RV32IZFINXZDINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 32
+; RV32IZFINXZDINX-NEXT: and a0, a2, a0
+; RV32IZFINXZDINX-NEXT: flt.d a3, a4, s0
+; RV32IZFINXZDINX-NEXT: neg a3, a3
+; RV32IZFINXZDINX-NEXT: or a0, a3, a0
+; RV32IZFINXZDINX-NEXT: and a1, a2, a1
+; RV32IZFINXZDINX-NEXT: or a1, a3, a1
+; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZFINXZDINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_floor_ui64:
@@ -300,18 +276,11 @@ define signext i32 @test_ceil_si32(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_ceil_si32:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.w.d a2, a0, rup
; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a0
; RV32IZFINXZDINX-NEXT: seqz a0, a0
; RV32IZFINXZDINX-NEXT: addi a0, a0, -1
; RV32IZFINXZDINX-NEXT: and a0, a0, a2
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_ceil_si32:
@@ -392,13 +361,11 @@ define i64 @test_ceil_si64(double %x) nounwind {
; RV32IZFINXZDINX-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: call ceil
-; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw s0, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw s1, 4(sp)
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI5_0)
; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI5_0+4)(a2)
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI5_0)(a2)
+; RV32IZFINXZDINX-NEXT: mv s0, a0
+; RV32IZFINXZDINX-NEXT: mv s1, a1
; RV32IZFINXZDINX-NEXT: fle.d s2, a2, s0
; RV32IZFINXZDINX-NEXT: neg s3, s2
; RV32IZFINXZDINX-NEXT: call __fixdfdi
@@ -457,18 +424,11 @@ define signext i32 @test_ceil_ui32(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_ceil_ui32:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.wu.d a2, a0, rup
; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a0
; RV32IZFINXZDINX-NEXT: seqz a0, a0
; RV32IZFINXZDINX-NEXT: addi a0, a0, -1
; RV32IZFINXZDINX-NEXT: and a0, a0, a2
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_ceil_ui32:
@@ -521,38 +481,30 @@ define i64 @test_ceil_ui64(double %x) nounwind {
;
; RV32IZFINXZDINX-LABEL: test_ceil_ui64:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -32
-; RV32IZFINXZDINX-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
+; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: call ceil
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw s0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw s1, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw s0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw s1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
+; RV32IZFINXZDINX-NEXT: mv s0, a0
+; RV32IZFINXZDINX-NEXT: mv s1, a1
+; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero
+; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI7_0)
+; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI7_0+4)(a4)
+; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI7_0)(a4)
; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
-; RV32IZFINXZDINX-NEXT: neg s2, a2
-; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
-; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI7_0)
-; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI7_0+4)(a2)
-; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI7_0)(a2)
-; RV32IZFINXZDINX-NEXT: and a0, s2, a0
-; RV32IZFINXZDINX-NEXT: flt.d a2, a2, s0
; RV32IZFINXZDINX-NEXT: neg a2, a2
-; RV32IZFINXZDINX-NEXT: or a0, a2, a0
-; RV32IZFINXZDINX-NEXT: and a1, s2, a1
-; RV32IZFINXZDINX-NEXT: or a1, a2, a1
-; RV32IZFINXZDINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 32
+; RV32IZFINXZDINX-NEXT: and a0, a2, a0
+; RV32IZFINXZDINX-NEXT: flt.d a3, a4, s0
+; RV32IZFINXZDINX-NEXT: neg a3, a3
+; RV32IZFINXZDINX-NEXT: or a0, a3, a0
+; RV32IZFINXZDINX-NEXT: and a1, a2, a1
+; RV32IZFINXZDINX-NEXT: or a1, a3, a1
+; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZFINXZDINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_ceil_ui64:
@@ -580,18 +532,11 @@ define signext i32 @test_trunc_si32(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_trunc_si32:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.w.d a2, a0, rtz
; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a0
; RV32IZFINXZDINX-NEXT: seqz a0, a0
; RV32IZFINXZDINX-NEXT: addi a0, a0, -1
; RV32IZFINXZDINX-NEXT: and a0, a0, a2
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_trunc_si32:
@@ -672,13 +617,11 @@ define i64 @test_trunc_si64(double %x) nounwind {
; RV32IZFINXZDINX-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: call trunc
-; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw s0, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw s1, 4(sp)
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI9_0)
; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI9_0+4)(a2)
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI9_0)(a2)
+; RV32IZFINXZDINX-NEXT: mv s0, a0
+; RV32IZFINXZDINX-NEXT: mv s1, a1
; RV32IZFINXZDINX-NEXT: fle.d s2, a2, s0
; RV32IZFINXZDINX-NEXT: neg s3, s2
; RV32IZFINXZDINX-NEXT: call __fixdfdi
@@ -737,18 +680,11 @@ define signext i32 @test_trunc_ui32(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_trunc_ui32:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.wu.d a2, a0, rtz
; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a0
; RV32IZFINXZDINX-NEXT: seqz a0, a0
; RV32IZFINXZDINX-NEXT: addi a0, a0, -1
; RV32IZFINXZDINX-NEXT: and a0, a0, a2
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_trunc_ui32:
@@ -801,38 +737,30 @@ define i64 @test_trunc_ui64(double %x) nounwind {
;
; RV32IZFINXZDINX-LABEL: test_trunc_ui64:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -32
-; RV32IZFINXZDINX-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
+; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: call trunc
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw s0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw s1, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw s0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw s1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
+; RV32IZFINXZDINX-NEXT: mv s0, a0
+; RV32IZFINXZDINX-NEXT: mv s1, a1
+; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero
+; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI11_0)
+; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI11_0+4)(a4)
+; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI11_0)(a4)
; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
-; RV32IZFINXZDINX-NEXT: neg s2, a2
-; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
-; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI11_0)
-; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI11_0+4)(a2)
-; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI11_0)(a2)
-; RV32IZFINXZDINX-NEXT: and a0, s2, a0
-; RV32IZFINXZDINX-NEXT: flt.d a2, a2, s0
; RV32IZFINXZDINX-NEXT: neg a2, a2
-; RV32IZFINXZDINX-NEXT: or a0, a2, a0
-; RV32IZFINXZDINX-NEXT: and a1, s2, a1
-; RV32IZFINXZDINX-NEXT: or a1, a2, a1
-; RV32IZFINXZDINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 32
+; RV32IZFINXZDINX-NEXT: and a0, a2, a0
+; RV32IZFINXZDINX-NEXT: flt.d a3, a4, s0
+; RV32IZFINXZDINX-NEXT: neg a3, a3
+; RV32IZFINXZDINX-NEXT: or a0, a3, a0
+; RV32IZFINXZDINX-NEXT: and a1, a2, a1
+; RV32IZFINXZDINX-NEXT: or a1, a3, a1
+; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZFINXZDINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_trunc_ui64:
@@ -860,18 +788,11 @@ define signext i32 @test_round_si32(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_round_si32:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.w.d a2, a0, rmm
; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a0
; RV32IZFINXZDINX-NEXT: seqz a0, a0
; RV32IZFINXZDINX-NEXT: addi a0, a0, -1
; RV32IZFINXZDINX-NEXT: and a0, a0, a2
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_round_si32:
@@ -952,13 +873,11 @@ define i64 @test_round_si64(double %x) nounwind {
; RV32IZFINXZDINX-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: call round
-; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw s0, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw s1, 4(sp)
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI13_0)
; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI13_0+4)(a2)
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI13_0)(a2)
+; RV32IZFINXZDINX-NEXT: mv s0, a0
+; RV32IZFINXZDINX-NEXT: mv s1, a1
; RV32IZFINXZDINX-NEXT: fle.d s2, a2, s0
; RV32IZFINXZDINX-NEXT: neg s3, s2
; RV32IZFINXZDINX-NEXT: call __fixdfdi
@@ -1017,18 +936,11 @@ define signext i32 @test_round_ui32(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_round_ui32:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.wu.d a2, a0, rmm
; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a0
; RV32IZFINXZDINX-NEXT: seqz a0, a0
; RV32IZFINXZDINX-NEXT: addi a0, a0, -1
; RV32IZFINXZDINX-NEXT: and a0, a0, a2
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_round_ui32:
@@ -1081,38 +993,30 @@ define i64 @test_round_ui64(double %x) nounwind {
;
; RV32IZFINXZDINX-LABEL: test_round_ui64:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -32
-; RV32IZFINXZDINX-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
+; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: call round
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw s0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw s1, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw s0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw s1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
+; RV32IZFINXZDINX-NEXT: mv s0, a0
+; RV32IZFINXZDINX-NEXT: mv s1, a1
+; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero
+; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI15_0)
+; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI15_0+4)(a4)
+; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI15_0)(a4)
; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
-; RV32IZFINXZDINX-NEXT: neg s2, a2
-; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
-; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI15_0)
-; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI15_0+4)(a2)
-; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI15_0)(a2)
-; RV32IZFINXZDINX-NEXT: and a0, s2, a0
-; RV32IZFINXZDINX-NEXT: flt.d a2, a2, s0
; RV32IZFINXZDINX-NEXT: neg a2, a2
-; RV32IZFINXZDINX-NEXT: or a0, a2, a0
-; RV32IZFINXZDINX-NEXT: and a1, s2, a1
-; RV32IZFINXZDINX-NEXT: or a1, a2, a1
-; RV32IZFINXZDINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 32
+; RV32IZFINXZDINX-NEXT: and a0, a2, a0
+; RV32IZFINXZDINX-NEXT: flt.d a3, a4, s0
+; RV32IZFINXZDINX-NEXT: neg a3, a3
+; RV32IZFINXZDINX-NEXT: or a0, a3, a0
+; RV32IZFINXZDINX-NEXT: and a1, a2, a1
+; RV32IZFINXZDINX-NEXT: or a1, a3, a1
+; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZFINXZDINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_round_ui64:
@@ -1140,18 +1044,11 @@ define signext i32 @test_roundeven_si32(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_roundeven_si32:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.w.d a2, a0, rne
; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a0
; RV32IZFINXZDINX-NEXT: seqz a0, a0
; RV32IZFINXZDINX-NEXT: addi a0, a0, -1
; RV32IZFINXZDINX-NEXT: and a0, a0, a2
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_roundeven_si32:
@@ -1232,13 +1129,11 @@ define i64 @test_roundeven_si64(double %x) nounwind {
; RV32IZFINXZDINX-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: call roundeven
-; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw s0, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw s1, 4(sp)
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI17_0)
; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI17_0+4)(a2)
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI17_0)(a2)
+; RV32IZFINXZDINX-NEXT: mv s0, a0
+; RV32IZFINXZDINX-NEXT: mv s1, a1
; RV32IZFINXZDINX-NEXT: fle.d s2, a2, s0
; RV32IZFINXZDINX-NEXT: neg s3, s2
; RV32IZFINXZDINX-NEXT: call __fixdfdi
@@ -1297,18 +1192,11 @@ define signext i32 @test_roundeven_ui32(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_roundeven_ui32:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.wu.d a2, a0, rne
; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a0
; RV32IZFINXZDINX-NEXT: seqz a0, a0
; RV32IZFINXZDINX-NEXT: addi a0, a0, -1
; RV32IZFINXZDINX-NEXT: and a0, a0, a2
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_roundeven_ui32:
@@ -1361,38 +1249,30 @@ define i64 @test_roundeven_ui64(double %x) nounwind {
;
; RV32IZFINXZDINX-LABEL: test_roundeven_ui64:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -32
-; RV32IZFINXZDINX-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
+; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: call roundeven
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw s0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw s1, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw s0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw s1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
+; RV32IZFINXZDINX-NEXT: mv s0, a0
+; RV32IZFINXZDINX-NEXT: mv s1, a1
+; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero
+; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI19_0)
+; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI19_0+4)(a4)
+; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI19_0)(a4)
; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
-; RV32IZFINXZDINX-NEXT: neg s2, a2
-; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
-; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI19_0)
-; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI19_0+4)(a2)
-; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI19_0)(a2)
-; RV32IZFINXZDINX-NEXT: and a0, s2, a0
-; RV32IZFINXZDINX-NEXT: flt.d a2, a2, s0
; RV32IZFINXZDINX-NEXT: neg a2, a2
-; RV32IZFINXZDINX-NEXT: or a0, a2, a0
-; RV32IZFINXZDINX-NEXT: and a1, s2, a1
-; RV32IZFINXZDINX-NEXT: or a1, a2, a1
-; RV32IZFINXZDINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 32
+; RV32IZFINXZDINX-NEXT: and a0, a2, a0
+; RV32IZFINXZDINX-NEXT: flt.d a3, a4, s0
+; RV32IZFINXZDINX-NEXT: neg a3, a3
+; RV32IZFINXZDINX-NEXT: or a0, a3, a0
+; RV32IZFINXZDINX-NEXT: and a1, a2, a1
+; RV32IZFINXZDINX-NEXT: or a1, a3, a1
+; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZFINXZDINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_roundeven_ui64:
@@ -1420,18 +1300,11 @@ define signext i32 @test_rint_si32(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_rint_si32:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.w.d a2, a0
; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a0
; RV32IZFINXZDINX-NEXT: seqz a0, a0
; RV32IZFINXZDINX-NEXT: addi a0, a0, -1
; RV32IZFINXZDINX-NEXT: and a0, a0, a2
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_rint_si32:
@@ -1512,13 +1385,11 @@ define i64 @test_rint_si64(double %x) nounwind {
; RV32IZFINXZDINX-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: call rint
-; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT: lw s0, 0(sp)
-; RV32IZFINXZDINX-NEXT: lw s1, 4(sp)
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI21_0)
; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI21_0+4)(a2)
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI21_0)(a2)
+; RV32IZFINXZDINX-NEXT: mv s0, a0
+; RV32IZFINXZDINX-NEXT: mv s1, a1
; RV32IZFINXZDINX-NEXT: fle.d s2, a2, s0
; RV32IZFINXZDINX-NEXT: neg s3, s2
; RV32IZFINXZDINX-NEXT: call __fixdfdi
@@ -1577,18 +1448,11 @@ define signext i32 @test_rint_ui32(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_rint_ui32:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.wu.d a2, a0
; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a0
; RV32IZFINXZDINX-NEXT: seqz a0, a0
; RV32IZFINXZDINX-NEXT: addi a0, a0, -1
; RV32IZFINXZDINX-NEXT: and a0, a0, a2
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_rint_ui32:
@@ -1641,38 +1505,30 @@ define i64 @test_rint_ui64(double %x) nounwind {
;
; RV32IZFINXZDINX-LABEL: test_rint_ui64:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -32
-; RV32IZFINXZDINX-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
+; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: call rint
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw s0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw s1, 12(sp)
-; RV32IZFINXZDINX-NEXT: sw s0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw s1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
+; RV32IZFINXZDINX-NEXT: mv s0, a0
+; RV32IZFINXZDINX-NEXT: mv s1, a1
+; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero
+; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI23_0)
+; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI23_0+4)(a4)
+; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI23_0)(a4)
; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
-; RV32IZFINXZDINX-NEXT: neg s2, a2
-; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
-; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI23_0)
-; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI23_0+4)(a2)
-; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI23_0)(a2)
-; RV32IZFINXZDINX-NEXT: and a0, s2, a0
-; RV32IZFINXZDINX-NEXT: flt.d a2, a2, s0
; RV32IZFINXZDINX-NEXT: neg a2, a2
-; RV32IZFINXZDINX-NEXT: or a0, a2, a0
-; RV32IZFINXZDINX-NEXT: and a1, s2, a1
-; RV32IZFINXZDINX-NEXT: or a1, a2, a1
-; RV32IZFINXZDINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 32
+; RV32IZFINXZDINX-NEXT: and a0, a2, a0
+; RV32IZFINXZDINX-NEXT: flt.d a3, a4, s0
+; RV32IZFINXZDINX-NEXT: neg a3, a3
+; RV32IZFINXZDINX-NEXT: or a0, a3, a0
+; RV32IZFINXZDINX-NEXT: and a1, a2, a1
+; RV32IZFINXZDINX-NEXT: or a1, a3, a1
+; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZFINXZDINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_rint_ui64:
diff --git a/llvm/test/CodeGen/RISCV/double-round-conv.ll b/llvm/test/CodeGen/RISCV/double-round-conv.ll
index 094a4105de71c3..d84d80a4a10e92 100644
--- a/llvm/test/CodeGen/RISCV/double-round-conv.ll
+++ b/llvm/test/CodeGen/RISCV/double-round-conv.ll
@@ -21,14 +21,7 @@ define signext i8 @test_floor_si8(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_floor_si8:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rdn
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_floor_si8:
@@ -53,14 +46,7 @@ define signext i16 @test_floor_si16(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_floor_si16:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rdn
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_floor_si16:
@@ -80,14 +66,7 @@ define signext i32 @test_floor_si32(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_floor_si32:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rdn
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_floor_si32:
@@ -151,14 +130,7 @@ define zeroext i8 @test_floor_ui8(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_floor_ui8:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rdn
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_floor_ui8:
@@ -183,14 +155,7 @@ define zeroext i16 @test_floor_ui16(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_floor_ui16:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rdn
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_floor_ui16:
@@ -210,14 +175,7 @@ define signext i32 @test_floor_ui32(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_floor_ui32:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rdn
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_floor_ui32:
@@ -281,14 +239,7 @@ define signext i8 @test_ceil_si8(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_ceil_si8:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rup
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_ceil_si8:
@@ -313,14 +264,7 @@ define signext i16 @test_ceil_si16(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_ceil_si16:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rup
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_ceil_si16:
@@ -340,14 +284,7 @@ define signext i32 @test_ceil_si32(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_ceil_si32:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rup
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_ceil_si32:
@@ -411,14 +348,7 @@ define zeroext i8 @test_ceil_ui8(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_ceil_ui8:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rup
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_ceil_ui8:
@@ -443,14 +373,7 @@ define zeroext i16 @test_ceil_ui16(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_ceil_ui16:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rup
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_ceil_ui16:
@@ -470,14 +393,7 @@ define signext i32 @test_ceil_ui32(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_ceil_ui32:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rup
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_ceil_ui32:
@@ -541,14 +457,7 @@ define signext i8 @test_trunc_si8(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_trunc_si8:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rtz
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_trunc_si8:
@@ -573,14 +482,7 @@ define signext i16 @test_trunc_si16(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_trunc_si16:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rtz
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_trunc_si16:
@@ -600,14 +502,7 @@ define signext i32 @test_trunc_si32(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_trunc_si32:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rtz
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_trunc_si32:
@@ -671,14 +566,7 @@ define zeroext i8 @test_trunc_ui8(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_trunc_ui8:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_trunc_ui8:
@@ -703,14 +591,7 @@ define zeroext i16 @test_trunc_ui16(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_trunc_ui16:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_trunc_ui16:
@@ -730,14 +611,7 @@ define signext i32 @test_trunc_ui32(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_trunc_ui32:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_trunc_ui32:
@@ -801,14 +675,7 @@ define signext i8 @test_round_si8(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_round_si8:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rmm
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_round_si8:
@@ -833,14 +700,7 @@ define signext i16 @test_round_si16(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_round_si16:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rmm
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_round_si16:
@@ -860,14 +720,7 @@ define signext i32 @test_round_si32(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_round_si32:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rmm
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_round_si32:
@@ -931,14 +784,7 @@ define zeroext i8 @test_round_ui8(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_round_ui8:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rmm
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_round_ui8:
@@ -963,14 +809,7 @@ define zeroext i16 @test_round_ui16(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_round_ui16:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rmm
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_round_ui16:
@@ -990,14 +829,7 @@ define signext i32 @test_round_ui32(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_round_ui32:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rmm
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_round_ui32:
@@ -1061,14 +893,7 @@ define signext i8 @test_roundeven_si8(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_roundeven_si8:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rne
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_roundeven_si8:
@@ -1093,14 +918,7 @@ define signext i16 @test_roundeven_si16(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_roundeven_si16:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rne
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_roundeven_si16:
@@ -1120,14 +938,7 @@ define signext i32 @test_roundeven_si32(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_roundeven_si32:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rne
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_roundeven_si32:
@@ -1191,14 +1002,7 @@ define zeroext i8 @test_roundeven_ui8(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_roundeven_ui8:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rne
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_roundeven_ui8:
@@ -1223,14 +1027,7 @@ define zeroext i16 @test_roundeven_ui16(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_roundeven_ui16:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rne
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_roundeven_ui16:
@@ -1250,14 +1047,7 @@ define signext i32 @test_roundeven_ui32(double %x) {
;
; RV32IZFINXZDINX-LABEL: test_roundeven_ui32:
; RV32IZFINXZDINX: # %bb.0:
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
-; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rne
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_roundeven_ui32:
diff --git a/llvm/test/CodeGen/RISCV/double-select-fcmp.ll b/llvm/test/CodeGen/RISCV/double-select-fcmp.ll
index 766da3680ffc0d..654a4609caa23f 100644
--- a/llvm/test/CodeGen/RISCV/double-select-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/double-select-fcmp.ll
@@ -41,26 +41,12 @@ define double @select_fcmp_oeq(double %a, double %b) nounwind {
;
; CHECKRV32ZDINX-LABEL: select_fcmp_oeq:
; CHECKRV32ZDINX: # %bb.0:
-; CHECKRV32ZDINX-NEXT: addi sp, sp, -16
-; CHECKRV32ZDINX-NEXT: sw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a3, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a3, 12(sp)
-; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a1, 12(sp)
; CHECKRV32ZDINX-NEXT: feq.d a4, a0, a2
; CHECKRV32ZDINX-NEXT: bnez a4, .LBB1_2
; CHECKRV32ZDINX-NEXT: # %bb.1:
; CHECKRV32ZDINX-NEXT: mv a0, a2
; CHECKRV32ZDINX-NEXT: mv a1, a3
; CHECKRV32ZDINX-NEXT: .LBB1_2:
-; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: addi sp, sp, 16
; CHECKRV32ZDINX-NEXT: ret
;
; CHECKRV64ZDINX-LABEL: select_fcmp_oeq:
@@ -88,26 +74,12 @@ define double @select_fcmp_ogt(double %a, double %b) nounwind {
;
; CHECKRV32ZDINX-LABEL: select_fcmp_ogt:
; CHECKRV32ZDINX: # %bb.0:
-; CHECKRV32ZDINX-NEXT: addi sp, sp, -16
-; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: sw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a3, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a3, 12(sp)
; CHECKRV32ZDINX-NEXT: flt.d a4, a2, a0
; CHECKRV32ZDINX-NEXT: bnez a4, .LBB2_2
; CHECKRV32ZDINX-NEXT: # %bb.1:
; CHECKRV32ZDINX-NEXT: mv a0, a2
; CHECKRV32ZDINX-NEXT: mv a1, a3
; CHECKRV32ZDINX-NEXT: .LBB2_2:
-; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: addi sp, sp, 16
; CHECKRV32ZDINX-NEXT: ret
;
; CHECKRV64ZDINX-LABEL: select_fcmp_ogt:
@@ -135,26 +107,12 @@ define double @select_fcmp_oge(double %a, double %b) nounwind {
;
; CHECKRV32ZDINX-LABEL: select_fcmp_oge:
; CHECKRV32ZDINX: # %bb.0:
-; CHECKRV32ZDINX-NEXT: addi sp, sp, -16
-; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: sw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a3, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a3, 12(sp)
; CHECKRV32ZDINX-NEXT: fle.d a4, a2, a0
; CHECKRV32ZDINX-NEXT: bnez a4, .LBB3_2
; CHECKRV32ZDINX-NEXT: # %bb.1:
; CHECKRV32ZDINX-NEXT: mv a0, a2
; CHECKRV32ZDINX-NEXT: mv a1, a3
; CHECKRV32ZDINX-NEXT: .LBB3_2:
-; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: addi sp, sp, 16
; CHECKRV32ZDINX-NEXT: ret
;
; CHECKRV64ZDINX-LABEL: select_fcmp_oge:
@@ -182,26 +140,12 @@ define double @select_fcmp_olt(double %a, double %b) nounwind {
;
; CHECKRV32ZDINX-LABEL: select_fcmp_olt:
; CHECKRV32ZDINX: # %bb.0:
-; CHECKRV32ZDINX-NEXT: addi sp, sp, -16
-; CHECKRV32ZDINX-NEXT: sw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a3, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a3, 12(sp)
-; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a1, 12(sp)
; CHECKRV32ZDINX-NEXT: flt.d a4, a0, a2
; CHECKRV32ZDINX-NEXT: bnez a4, .LBB4_2
; CHECKRV32ZDINX-NEXT: # %bb.1:
; CHECKRV32ZDINX-NEXT: mv a0, a2
; CHECKRV32ZDINX-NEXT: mv a1, a3
; CHECKRV32ZDINX-NEXT: .LBB4_2:
-; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: addi sp, sp, 16
; CHECKRV32ZDINX-NEXT: ret
;
; CHECKRV64ZDINX-LABEL: select_fcmp_olt:
@@ -229,26 +173,12 @@ define double @select_fcmp_ole(double %a, double %b) nounwind {
;
; CHECKRV32ZDINX-LABEL: select_fcmp_ole:
; CHECKRV32ZDINX: # %bb.0:
-; CHECKRV32ZDINX-NEXT: addi sp, sp, -16
-; CHECKRV32ZDINX-NEXT: sw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a3, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a3, 12(sp)
-; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a1, 12(sp)
; CHECKRV32ZDINX-NEXT: fle.d a4, a0, a2
; CHECKRV32ZDINX-NEXT: bnez a4, .LBB5_2
; CHECKRV32ZDINX-NEXT: # %bb.1:
; CHECKRV32ZDINX-NEXT: mv a0, a2
; CHECKRV32ZDINX-NEXT: mv a1, a3
; CHECKRV32ZDINX-NEXT: .LBB5_2:
-; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: addi sp, sp, 16
; CHECKRV32ZDINX-NEXT: ret
;
; CHECKRV64ZDINX-LABEL: select_fcmp_ole:
@@ -278,15 +208,6 @@ define double @select_fcmp_one(double %a, double %b) nounwind {
;
; CHECKRV32ZDINX-LABEL: select_fcmp_one:
; CHECKRV32ZDINX: # %bb.0:
-; CHECKRV32ZDINX-NEXT: addi sp, sp, -16
-; CHECKRV32ZDINX-NEXT: sw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a3, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a3, 12(sp)
-; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a1, 12(sp)
; CHECKRV32ZDINX-NEXT: flt.d a4, a0, a2
; CHECKRV32ZDINX-NEXT: flt.d a5, a2, a0
; CHECKRV32ZDINX-NEXT: or a4, a5, a4
@@ -295,11 +216,6 @@ define double @select_fcmp_one(double %a, double %b) nounwind {
; CHECKRV32ZDINX-NEXT: mv a0, a2
; CHECKRV32ZDINX-NEXT: mv a1, a3
; CHECKRV32ZDINX-NEXT: .LBB6_2:
-; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: addi sp, sp, 16
; CHECKRV32ZDINX-NEXT: ret
;
; CHECKRV64ZDINX-LABEL: select_fcmp_one:
@@ -331,15 +247,6 @@ define double @select_fcmp_ord(double %a, double %b) nounwind {
;
; CHECKRV32ZDINX-LABEL: select_fcmp_ord:
; CHECKRV32ZDINX: # %bb.0:
-; CHECKRV32ZDINX-NEXT: addi sp, sp, -16
-; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: sw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a3, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a3, 12(sp)
; CHECKRV32ZDINX-NEXT: feq.d a4, a2, a2
; CHECKRV32ZDINX-NEXT: feq.d a5, a0, a0
; CHECKRV32ZDINX-NEXT: and a4, a5, a4
@@ -348,11 +255,6 @@ define double @select_fcmp_ord(double %a, double %b) nounwind {
; CHECKRV32ZDINX-NEXT: mv a0, a2
; CHECKRV32ZDINX-NEXT: mv a1, a3
; CHECKRV32ZDINX-NEXT: .LBB7_2:
-; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: addi sp, sp, 16
; CHECKRV32ZDINX-NEXT: ret
;
; CHECKRV64ZDINX-LABEL: select_fcmp_ord:
@@ -384,15 +286,6 @@ define double @select_fcmp_ueq(double %a, double %b) nounwind {
;
; CHECKRV32ZDINX-LABEL: select_fcmp_ueq:
; CHECKRV32ZDINX: # %bb.0:
-; CHECKRV32ZDINX-NEXT: addi sp, sp, -16
-; CHECKRV32ZDINX-NEXT: sw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a3, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a3, 12(sp)
-; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a1, 12(sp)
; CHECKRV32ZDINX-NEXT: flt.d a4, a0, a2
; CHECKRV32ZDINX-NEXT: flt.d a5, a2, a0
; CHECKRV32ZDINX-NEXT: or a4, a5, a4
@@ -401,11 +294,6 @@ define double @select_fcmp_ueq(double %a, double %b) nounwind {
; CHECKRV32ZDINX-NEXT: mv a0, a2
; CHECKRV32ZDINX-NEXT: mv a1, a3
; CHECKRV32ZDINX-NEXT: .LBB8_2:
-; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: addi sp, sp, 16
; CHECKRV32ZDINX-NEXT: ret
;
; CHECKRV64ZDINX-LABEL: select_fcmp_ueq:
@@ -435,26 +323,12 @@ define double @select_fcmp_ugt(double %a, double %b) nounwind {
;
; CHECKRV32ZDINX-LABEL: select_fcmp_ugt:
; CHECKRV32ZDINX: # %bb.0:
-; CHECKRV32ZDINX-NEXT: addi sp, sp, -16
-; CHECKRV32ZDINX-NEXT: sw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a3, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a3, 12(sp)
-; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a1, 12(sp)
; CHECKRV32ZDINX-NEXT: fle.d a4, a0, a2
; CHECKRV32ZDINX-NEXT: beqz a4, .LBB9_2
; CHECKRV32ZDINX-NEXT: # %bb.1:
; CHECKRV32ZDINX-NEXT: mv a0, a2
; CHECKRV32ZDINX-NEXT: mv a1, a3
; CHECKRV32ZDINX-NEXT: .LBB9_2:
-; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: addi sp, sp, 16
; CHECKRV32ZDINX-NEXT: ret
;
; CHECKRV64ZDINX-LABEL: select_fcmp_ugt:
@@ -482,26 +356,12 @@ define double @select_fcmp_uge(double %a, double %b) nounwind {
;
; CHECKRV32ZDINX-LABEL: select_fcmp_uge:
; CHECKRV32ZDINX: # %bb.0:
-; CHECKRV32ZDINX-NEXT: addi sp, sp, -16
-; CHECKRV32ZDINX-NEXT: sw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a3, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a3, 12(sp)
-; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a1, 12(sp)
; CHECKRV32ZDINX-NEXT: flt.d a4, a0, a2
; CHECKRV32ZDINX-NEXT: beqz a4, .LBB10_2
; CHECKRV32ZDINX-NEXT: # %bb.1:
; CHECKRV32ZDINX-NEXT: mv a0, a2
; CHECKRV32ZDINX-NEXT: mv a1, a3
; CHECKRV32ZDINX-NEXT: .LBB10_2:
-; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: addi sp, sp, 16
; CHECKRV32ZDINX-NEXT: ret
;
; CHECKRV64ZDINX-LABEL: select_fcmp_uge:
@@ -529,26 +389,12 @@ define double @select_fcmp_ult(double %a, double %b) nounwind {
;
; CHECKRV32ZDINX-LABEL: select_fcmp_ult:
; CHECKRV32ZDINX: # %bb.0:
-; CHECKRV32ZDINX-NEXT: addi sp, sp, -16
-; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: sw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a3, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a3, 12(sp)
; CHECKRV32ZDINX-NEXT: fle.d a4, a2, a0
; CHECKRV32ZDINX-NEXT: beqz a4, .LBB11_2
; CHECKRV32ZDINX-NEXT: # %bb.1:
; CHECKRV32ZDINX-NEXT: mv a0, a2
; CHECKRV32ZDINX-NEXT: mv a1, a3
; CHECKRV32ZDINX-NEXT: .LBB11_2:
-; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: addi sp, sp, 16
; CHECKRV32ZDINX-NEXT: ret
;
; CHECKRV64ZDINX-LABEL: select_fcmp_ult:
@@ -576,26 +422,12 @@ define double @select_fcmp_ule(double %a, double %b) nounwind {
;
; CHECKRV32ZDINX-LABEL: select_fcmp_ule:
; CHECKRV32ZDINX: # %bb.0:
-; CHECKRV32ZDINX-NEXT: addi sp, sp, -16
-; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: sw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a3, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a3, 12(sp)
; CHECKRV32ZDINX-NEXT: flt.d a4, a2, a0
; CHECKRV32ZDINX-NEXT: beqz a4, .LBB12_2
; CHECKRV32ZDINX-NEXT: # %bb.1:
; CHECKRV32ZDINX-NEXT: mv a0, a2
; CHECKRV32ZDINX-NEXT: mv a1, a3
; CHECKRV32ZDINX-NEXT: .LBB12_2:
-; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: addi sp, sp, 16
; CHECKRV32ZDINX-NEXT: ret
;
; CHECKRV64ZDINX-LABEL: select_fcmp_ule:
@@ -623,26 +455,12 @@ define double @select_fcmp_une(double %a, double %b) nounwind {
;
; CHECKRV32ZDINX-LABEL: select_fcmp_une:
; CHECKRV32ZDINX: # %bb.0:
-; CHECKRV32ZDINX-NEXT: addi sp, sp, -16
-; CHECKRV32ZDINX-NEXT: sw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a3, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a3, 12(sp)
-; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a1, 12(sp)
; CHECKRV32ZDINX-NEXT: feq.d a4, a0, a2
; CHECKRV32ZDINX-NEXT: beqz a4, .LBB13_2
; CHECKRV32ZDINX-NEXT: # %bb.1:
; CHECKRV32ZDINX-NEXT: mv a0, a2
; CHECKRV32ZDINX-NEXT: mv a1, a3
; CHECKRV32ZDINX-NEXT: .LBB13_2:
-; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: addi sp, sp, 16
; CHECKRV32ZDINX-NEXT: ret
;
; CHECKRV64ZDINX-LABEL: select_fcmp_une:
@@ -672,15 +490,6 @@ define double @select_fcmp_uno(double %a, double %b) nounwind {
;
; CHECKRV32ZDINX-LABEL: select_fcmp_uno:
; CHECKRV32ZDINX: # %bb.0:
-; CHECKRV32ZDINX-NEXT: addi sp, sp, -16
-; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: sw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a3, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a3, 12(sp)
; CHECKRV32ZDINX-NEXT: feq.d a4, a2, a2
; CHECKRV32ZDINX-NEXT: feq.d a5, a0, a0
; CHECKRV32ZDINX-NEXT: and a4, a5, a4
@@ -689,11 +498,6 @@ define double @select_fcmp_uno(double %a, double %b) nounwind {
; CHECKRV32ZDINX-NEXT: mv a0, a2
; CHECKRV32ZDINX-NEXT: mv a1, a3
; CHECKRV32ZDINX-NEXT: .LBB14_2:
-; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: addi sp, sp, 16
; CHECKRV32ZDINX-NEXT: ret
;
; CHECKRV64ZDINX-LABEL: select_fcmp_uno:
@@ -741,22 +545,12 @@ define i32 @i32_select_fcmp_oeq(double %a, double %b, i32 %c, i32 %d) nounwind {
;
; CHECKRV32ZDINX-LABEL: i32_select_fcmp_oeq:
; CHECKRV32ZDINX: # %bb.0:
-; CHECKRV32ZDINX-NEXT: addi sp, sp, -16
-; CHECKRV32ZDINX-NEXT: sw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a3, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a3, 12(sp)
-; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a1, 12(sp)
; CHECKRV32ZDINX-NEXT: feq.d a1, a0, a2
; CHECKRV32ZDINX-NEXT: mv a0, a4
; CHECKRV32ZDINX-NEXT: bnez a1, .LBB16_2
; CHECKRV32ZDINX-NEXT: # %bb.1:
; CHECKRV32ZDINX-NEXT: mv a0, a5
; CHECKRV32ZDINX-NEXT: .LBB16_2:
-; CHECKRV32ZDINX-NEXT: addi sp, sp, 16
; CHECKRV32ZDINX-NEXT: ret
;
; CHECKRV64ZDINX-LABEL: i32_select_fcmp_oeq:
@@ -783,20 +577,9 @@ define i32 @select_fcmp_oeq_1_2(double %a, double %b) {
;
; CHECKRV32ZDINX-LABEL: select_fcmp_oeq_1_2:
; CHECKRV32ZDINX: # %bb.0:
-; CHECKRV32ZDINX-NEXT: addi sp, sp, -16
-; CHECKRV32ZDINX-NEXT: .cfi_def_cfa_offset 16
-; CHECKRV32ZDINX-NEXT: sw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a3, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a3, 12(sp)
-; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a1, 12(sp)
; CHECKRV32ZDINX-NEXT: feq.d a0, a0, a2
; CHECKRV32ZDINX-NEXT: li a1, 2
; CHECKRV32ZDINX-NEXT: sub a0, a1, a0
-; CHECKRV32ZDINX-NEXT: addi sp, sp, 16
; CHECKRV32ZDINX-NEXT: ret
;
; CHECKRV64ZDINX-LABEL: select_fcmp_oeq_1_2:
@@ -819,18 +602,8 @@ define signext i32 @select_fcmp_uge_negone_zero(double %a, double %b) nounwind {
;
; CHECKRV32ZDINX-LABEL: select_fcmp_uge_negone_zero:
; CHECKRV32ZDINX: # %bb.0:
-; CHECKRV32ZDINX-NEXT: addi sp, sp, -16
-; CHECKRV32ZDINX-NEXT: sw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a3, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a3, 12(sp)
-; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a1, 12(sp)
; CHECKRV32ZDINX-NEXT: fle.d a0, a0, a2
; CHECKRV32ZDINX-NEXT: addi a0, a0, -1
-; CHECKRV32ZDINX-NEXT: addi sp, sp, 16
; CHECKRV32ZDINX-NEXT: ret
;
; CHECKRV64ZDINX-LABEL: select_fcmp_uge_negone_zero:
@@ -852,18 +625,8 @@ define signext i32 @select_fcmp_uge_1_2(double %a, double %b) nounwind {
;
; CHECKRV32ZDINX-LABEL: select_fcmp_uge_1_2:
; CHECKRV32ZDINX: # %bb.0:
-; CHECKRV32ZDINX-NEXT: addi sp, sp, -16
-; CHECKRV32ZDINX-NEXT: sw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a3, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a3, 12(sp)
-; CHECKRV32ZDINX-NEXT: sw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: sw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT: lw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT: lw a1, 12(sp)
; CHECKRV32ZDINX-NEXT: fle.d a0, a0, a2
; CHECKRV32ZDINX-NEXT: addi a0, a0, 1
-; CHECKRV32ZDINX-NEXT: addi sp, sp, 16
; CHECKRV32ZDINX-NEXT: ret
;
; CHECKRV64ZDINX-LABEL: select_fcmp_uge_1_2:
diff --git a/llvm/test/CodeGen/RISCV/double-select-icmp.ll b/llvm/test/CodeGen/RISCV/double-select-icmp.ll
index d864ff51b4669b..929ffc578f5b43 100644
--- a/llvm/test/CodeGen/RISCV/double-select-icmp.ll
+++ b/llvm/test/CodeGen/RISCV/double-select-icmp.ll
@@ -20,24 +20,13 @@ define double @select_icmp_eq(i32 signext %a, i32 signext %b, double %c, double
;
; RV32ZDINX-LABEL: select_icmp_eq:
; RV32ZDINX: # %bb.0:
-; RV32ZDINX-NEXT: addi sp, sp, -16
-; RV32ZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32ZDINX-NEXT: sw a4, 8(sp)
-; RV32ZDINX-NEXT: sw a5, 12(sp)
-; RV32ZDINX-NEXT: lw a4, 8(sp)
-; RV32ZDINX-NEXT: lw a5, 12(sp)
-; RV32ZDINX-NEXT: sw a2, 8(sp)
-; RV32ZDINX-NEXT: sw a3, 12(sp)
-; RV32ZDINX-NEXT: bne a0, a1, .LBB0_2
+; RV32ZDINX-NEXT: beq a0, a1, .LBB0_2
; RV32ZDINX-NEXT: # %bb.1:
-; RV32ZDINX-NEXT: lw a4, 8(sp)
-; RV32ZDINX-NEXT: lw a5, 12(sp)
+; RV32ZDINX-NEXT: mv a2, a4
+; RV32ZDINX-NEXT: mv a3, a5
; RV32ZDINX-NEXT: .LBB0_2:
-; RV32ZDINX-NEXT: sw a4, 8(sp)
-; RV32ZDINX-NEXT: sw a5, 12(sp)
-; RV32ZDINX-NEXT: lw a0, 8(sp)
-; RV32ZDINX-NEXT: lw a1, 12(sp)
-; RV32ZDINX-NEXT: addi sp, sp, 16
+; RV32ZDINX-NEXT: mv a0, a2
+; RV32ZDINX-NEXT: mv a1, a3
; RV32ZDINX-NEXT: ret
;
; RV64ZDINX-LABEL: select_icmp_eq:
@@ -64,24 +53,13 @@ define double @select_icmp_ne(i32 signext %a, i32 signext %b, double %c, double
;
; RV32ZDINX-LABEL: select_icmp_ne:
; RV32ZDINX: # %bb.0:
-; RV32ZDINX-NEXT: addi sp, sp, -16
-; RV32ZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32ZDINX-NEXT: sw a4, 8(sp)
-; RV32ZDINX-NEXT: sw a5, 12(sp)
-; RV32ZDINX-NEXT: lw a4, 8(sp)
-; RV32ZDINX-NEXT: lw a5, 12(sp)
-; RV32ZDINX-NEXT: sw a2, 8(sp)
-; RV32ZDINX-NEXT: sw a3, 12(sp)
-; RV32ZDINX-NEXT: beq a0, a1, .LBB1_2
+; RV32ZDINX-NEXT: bne a0, a1, .LBB1_2
; RV32ZDINX-NEXT: # %bb.1:
-; RV32ZDINX-NEXT: lw a4, 8(sp)
-; RV32ZDINX-NEXT: lw a5, 12(sp)
+; RV32ZDINX-NEXT: mv a2, a4
+; RV32ZDINX-NEXT: mv a3, a5
; RV32ZDINX-NEXT: .LBB1_2:
-; RV32ZDINX-NEXT: sw a4, 8(sp)
-; RV32ZDINX-NEXT: sw a5, 12(sp)
-; RV32ZDINX-NEXT: lw a0, 8(sp)
-; RV32ZDINX-NEXT: lw a1, 12(sp)
-; RV32ZDINX-NEXT: addi sp, sp, 16
+; RV32ZDINX-NEXT: mv a0, a2
+; RV32ZDINX-NEXT: mv a1, a3
; RV32ZDINX-NEXT: ret
;
; RV64ZDINX-LABEL: select_icmp_ne:
@@ -108,24 +86,13 @@ define double @select_icmp_ugt(i32 signext %a, i32 signext %b, double %c, double
;
; RV32ZDINX-LABEL: select_icmp_ugt:
; RV32ZDINX: # %bb.0:
-; RV32ZDINX-NEXT: addi sp, sp, -16
-; RV32ZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32ZDINX-NEXT: sw a4, 8(sp)
-; RV32ZDINX-NEXT: sw a5, 12(sp)
-; RV32ZDINX-NEXT: lw a4, 8(sp)
-; RV32ZDINX-NEXT: lw a5, 12(sp)
-; RV32ZDINX-NEXT: sw a2, 8(sp)
-; RV32ZDINX-NEXT: sw a3, 12(sp)
-; RV32ZDINX-NEXT: bgeu a1, a0, .LBB2_2
+; RV32ZDINX-NEXT: bltu a1, a0, .LBB2_2
; RV32ZDINX-NEXT: # %bb.1:
-; RV32ZDINX-NEXT: lw a4, 8(sp)
-; RV32ZDINX-NEXT: lw a5, 12(sp)
+; RV32ZDINX-NEXT: mv a2, a4
+; RV32ZDINX-NEXT: mv a3, a5
; RV32ZDINX-NEXT: .LBB2_2:
-; RV32ZDINX-NEXT: sw a4, 8(sp)
-; RV32ZDINX-NEXT: sw a5, 12(sp)
-; RV32ZDINX-NEXT: lw a0, 8(sp)
-; RV32ZDINX-NEXT: lw a1, 12(sp)
-; RV32ZDINX-NEXT: addi sp, sp, 16
+; RV32ZDINX-NEXT: mv a0, a2
+; RV32ZDINX-NEXT: mv a1, a3
; RV32ZDINX-NEXT: ret
;
; RV64ZDINX-LABEL: select_icmp_ugt:
@@ -152,24 +119,13 @@ define double @select_icmp_uge(i32 signext %a, i32 signext %b, double %c, double
;
; RV32ZDINX-LABEL: select_icmp_uge:
; RV32ZDINX: # %bb.0:
-; RV32ZDINX-NEXT: addi sp, sp, -16
-; RV32ZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32ZDINX-NEXT: sw a4, 8(sp)
-; RV32ZDINX-NEXT: sw a5, 12(sp)
-; RV32ZDINX-NEXT: lw a4, 8(sp)
-; RV32ZDINX-NEXT: lw a5, 12(sp)
-; RV32ZDINX-NEXT: sw a2, 8(sp)
-; RV32ZDINX-NEXT: sw a3, 12(sp)
-; RV32ZDINX-NEXT: bltu a0, a1, .LBB3_2
+; RV32ZDINX-NEXT: bgeu a0, a1, .LBB3_2
; RV32ZDINX-NEXT: # %bb.1:
-; RV32ZDINX-NEXT: lw a4, 8(sp)
-; RV32ZDINX-NEXT: lw a5, 12(sp)
+; RV32ZDINX-NEXT: mv a2, a4
+; RV32ZDINX-NEXT: mv a3, a5
; RV32ZDINX-NEXT: .LBB3_2:
-; RV32ZDINX-NEXT: sw a4, 8(sp)
-; RV32ZDINX-NEXT: sw a5, 12(sp)
-; RV32ZDINX-NEXT: lw a0, 8(sp)
-; RV32ZDINX-NEXT: lw a1, 12(sp)
-; RV32ZDINX-NEXT: addi sp, sp, 16
+; RV32ZDINX-NEXT: mv a0, a2
+; RV32ZDINX-NEXT: mv a1, a3
; RV32ZDINX-NEXT: ret
;
; RV64ZDINX-LABEL: select_icmp_uge:
@@ -196,24 +152,13 @@ define double @select_icmp_ult(i32 signext %a, i32 signext %b, double %c, double
;
; RV32ZDINX-LABEL: select_icmp_ult:
; RV32ZDINX: # %bb.0:
-; RV32ZDINX-NEXT: addi sp, sp, -16
-; RV32ZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32ZDINX-NEXT: sw a4, 8(sp)
-; RV32ZDINX-NEXT: sw a5, 12(sp)
-; RV32ZDINX-NEXT: lw a4, 8(sp)
-; RV32ZDINX-NEXT: lw a5, 12(sp)
-; RV32ZDINX-NEXT: sw a2, 8(sp)
-; RV32ZDINX-NEXT: sw a3, 12(sp)
-; RV32ZDINX-NEXT: bgeu a0, a1, .LBB4_2
+; RV32ZDINX-NEXT: bltu a0, a1, .LBB4_2
; RV32ZDINX-NEXT: # %bb.1:
-; RV32ZDINX-NEXT: lw a4, 8(sp)
-; RV32ZDINX-NEXT: lw a5, 12(sp)
+; RV32ZDINX-NEXT: mv a2, a4
+; RV32ZDINX-NEXT: mv a3, a5
; RV32ZDINX-NEXT: .LBB4_2:
-; RV32ZDINX-NEXT: sw a4, 8(sp)
-; RV32ZDINX-NEXT: sw a5, 12(sp)
-; RV32ZDINX-NEXT: lw a0, 8(sp)
-; RV32ZDINX-NEXT: lw a1, 12(sp)
-; RV32ZDINX-NEXT: addi sp, sp, 16
+; RV32ZDINX-NEXT: mv a0, a2
+; RV32ZDINX-NEXT: mv a1, a3
; RV32ZDINX-NEXT: ret
;
; RV64ZDINX-LABEL: select_icmp_ult:
@@ -240,24 +185,13 @@ define double @select_icmp_ule(i32 signext %a, i32 signext %b, double %c, double
;
; RV32ZDINX-LABEL: select_icmp_ule:
; RV32ZDINX: # %bb.0:
-; RV32ZDINX-NEXT: addi sp, sp, -16
-; RV32ZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32ZDINX-NEXT: sw a4, 8(sp)
-; RV32ZDINX-NEXT: sw a5, 12(sp)
-; RV32ZDINX-NEXT: lw a4, 8(sp)
-; RV32ZDINX-NEXT: lw a5, 12(sp)
-; RV32ZDINX-NEXT: sw a2, 8(sp)
-; RV32ZDINX-NEXT: sw a3, 12(sp)
-; RV32ZDINX-NEXT: bltu a1, a0, .LBB5_2
+; RV32ZDINX-NEXT: bgeu a1, a0, .LBB5_2
; RV32ZDINX-NEXT: # %bb.1:
-; RV32ZDINX-NEXT: lw a4, 8(sp)
-; RV32ZDINX-NEXT: lw a5, 12(sp)
+; RV32ZDINX-NEXT: mv a2, a4
+; RV32ZDINX-NEXT: mv a3, a5
; RV32ZDINX-NEXT: .LBB5_2:
-; RV32ZDINX-NEXT: sw a4, 8(sp)
-; RV32ZDINX-NEXT: sw a5, 12(sp)
-; RV32ZDINX-NEXT: lw a0, 8(sp)
-; RV32ZDINX-NEXT: lw a1, 12(sp)
-; RV32ZDINX-NEXT: addi sp, sp, 16
+; RV32ZDINX-NEXT: mv a0, a2
+; RV32ZDINX-NEXT: mv a1, a3
; RV32ZDINX-NEXT: ret
;
; RV64ZDINX-LABEL: select_icmp_ule:
@@ -284,24 +218,13 @@ define double @select_icmp_sgt(i32 signext %a, i32 signext %b, double %c, double
;
; RV32ZDINX-LABEL: select_icmp_sgt:
; RV32ZDINX: # %bb.0:
-; RV32ZDINX-NEXT: addi sp, sp, -16
-; RV32ZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32ZDINX-NEXT: sw a4, 8(sp)
-; RV32ZDINX-NEXT: sw a5, 12(sp)
-; RV32ZDINX-NEXT: lw a4, 8(sp)
-; RV32ZDINX-NEXT: lw a5, 12(sp)
-; RV32ZDINX-NEXT: sw a2, 8(sp)
-; RV32ZDINX-NEXT: sw a3, 12(sp)
-; RV32ZDINX-NEXT: bge a1, a0, .LBB6_2
+; RV32ZDINX-NEXT: blt a1, a0, .LBB6_2
; RV32ZDINX-NEXT: # %bb.1:
-; RV32ZDINX-NEXT: lw a4, 8(sp)
-; RV32ZDINX-NEXT: lw a5, 12(sp)
+; RV32ZDINX-NEXT: mv a2, a4
+; RV32ZDINX-NEXT: mv a3, a5
; RV32ZDINX-NEXT: .LBB6_2:
-; RV32ZDINX-NEXT: sw a4, 8(sp)
-; RV32ZDINX-NEXT: sw a5, 12(sp)
-; RV32ZDINX-NEXT: lw a0, 8(sp)
-; RV32ZDINX-NEXT: lw a1, 12(sp)
-; RV32ZDINX-NEXT: addi sp, sp, 16
+; RV32ZDINX-NEXT: mv a0, a2
+; RV32ZDINX-NEXT: mv a1, a3
; RV32ZDINX-NEXT: ret
;
; RV64ZDINX-LABEL: select_icmp_sgt:
@@ -328,24 +251,13 @@ define double @select_icmp_sge(i32 signext %a, i32 signext %b, double %c, double
;
; RV32ZDINX-LABEL: select_icmp_sge:
; RV32ZDINX: # %bb.0:
-; RV32ZDINX-NEXT: addi sp, sp, -16
-; RV32ZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32ZDINX-NEXT: sw a4, 8(sp)
-; RV32ZDINX-NEXT: sw a5, 12(sp)
-; RV32ZDINX-NEXT: lw a4, 8(sp)
-; RV32ZDINX-NEXT: lw a5, 12(sp)
-; RV32ZDINX-NEXT: sw a2, 8(sp)
-; RV32ZDINX-NEXT: sw a3, 12(sp)
-; RV32ZDINX-NEXT: blt a0, a1, .LBB7_2
+; RV32ZDINX-NEXT: bge a0, a1, .LBB7_2
; RV32ZDINX-NEXT: # %bb.1:
-; RV32ZDINX-NEXT: lw a4, 8(sp)
-; RV32ZDINX-NEXT: lw a5, 12(sp)
+; RV32ZDINX-NEXT: mv a2, a4
+; RV32ZDINX-NEXT: mv a3, a5
; RV32ZDINX-NEXT: .LBB7_2:
-; RV32ZDINX-NEXT: sw a4, 8(sp)
-; RV32ZDINX-NEXT: sw a5, 12(sp)
-; RV32ZDINX-NEXT: lw a0, 8(sp)
-; RV32ZDINX-NEXT: lw a1, 12(sp)
-; RV32ZDINX-NEXT: addi sp, sp, 16
+; RV32ZDINX-NEXT: mv a0, a2
+; RV32ZDINX-NEXT: mv a1, a3
; RV32ZDINX-NEXT: ret
;
; RV64ZDINX-LABEL: select_icmp_sge:
@@ -372,24 +284,13 @@ define double @select_icmp_slt(i32 signext %a, i32 signext %b, double %c, double
;
; RV32ZDINX-LABEL: select_icmp_slt:
; RV32ZDINX: # %bb.0:
-; RV32ZDINX-NEXT: addi sp, sp, -16
-; RV32ZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32ZDINX-NEXT: sw a4, 8(sp)
-; RV32ZDINX-NEXT: sw a5, 12(sp)
-; RV32ZDINX-NEXT: lw a4, 8(sp)
-; RV32ZDINX-NEXT: lw a5, 12(sp)
-; RV32ZDINX-NEXT: sw a2, 8(sp)
-; RV32ZDINX-NEXT: sw a3, 12(sp)
-; RV32ZDINX-NEXT: bge a0, a1, .LBB8_2
+; RV32ZDINX-NEXT: blt a0, a1, .LBB8_2
; RV32ZDINX-NEXT: # %bb.1:
-; RV32ZDINX-NEXT: lw a4, 8(sp)
-; RV32ZDINX-NEXT: lw a5, 12(sp)
+; RV32ZDINX-NEXT: mv a2, a4
+; RV32ZDINX-NEXT: mv a3, a5
; RV32ZDINX-NEXT: .LBB8_2:
-; RV32ZDINX-NEXT: sw a4, 8(sp)
-; RV32ZDINX-NEXT: sw a5, 12(sp)
-; RV32ZDINX-NEXT: lw a0, 8(sp)
-; RV32ZDINX-NEXT: lw a1, 12(sp)
-; RV32ZDINX-NEXT: addi sp, sp, 16
+; RV32ZDINX-NEXT: mv a0, a2
+; RV32ZDINX-NEXT: mv a1, a3
; RV32ZDINX-NEXT: ret
;
; RV64ZDINX-LABEL: select_icmp_slt:
@@ -416,24 +317,13 @@ define double @select_icmp_sle(i32 signext %a, i32 signext %b, double %c, double
;
; RV32ZDINX-LABEL: select_icmp_sle:
; RV32ZDINX: # %bb.0:
-; RV32ZDINX-NEXT: addi sp, sp, -16
-; RV32ZDINX-NEXT: .cfi_def_cfa_offset 16
-; RV32ZDINX-NEXT: sw a4, 8(sp)
-; RV32ZDINX-NEXT: sw a5, 12(sp)
-; RV32ZDINX-NEXT: lw a4, 8(sp)
-; RV32ZDINX-NEXT: lw a5, 12(sp)
-; RV32ZDINX-NEXT: sw a2, 8(sp)
-; RV32ZDINX-NEXT: sw a3, 12(sp)
-; RV32ZDINX-NEXT: blt a1, a0, .LBB9_2
+; RV32ZDINX-NEXT: bge a1, a0, .LBB9_2
; RV32ZDINX-NEXT: # %bb.1:
-; RV32ZDINX-NEXT: lw a4, 8(sp)
-; RV32ZDINX-NEXT: lw a5, 12(sp)
+; RV32ZDINX-NEXT: mv a2, a4
+; RV32ZDINX-NEXT: mv a3, a5
; RV32ZDINX-NEXT: .LBB9_2:
-; RV32ZDINX-NEXT: sw a4, 8(sp)
-; RV32ZDINX-NEXT: sw a5, 12(sp)
-; RV32ZDINX-NEXT: lw a0, 8(sp)
-; RV32ZDINX-NEXT: lw a1, 12(sp)
-; RV32ZDINX-NEXT: addi sp, sp, 16
+; RV32ZDINX-NEXT: mv a0, a2
+; RV32ZDINX-NEXT: mv a1, a3
; RV32ZDINX-NEXT: ret
;
; RV64ZDINX-LABEL: select_icmp_sle:
@@ -458,15 +348,8 @@ define double @select_icmp_slt_one(i32 signext %a) {
;
; RV32ZDINX-LABEL: select_icmp_slt_one:
; RV32ZDINX: # %bb.0:
-; RV32ZDINX-NEXT: addi sp, sp, -16
-; RV32ZDINX-NEXT: .cfi_def_cfa_offset 16
; RV32ZDINX-NEXT: slti a0, a0, 1
; RV32ZDINX-NEXT: fcvt.d.w a0, a0
-; RV32ZDINX-NEXT: sw a0, 8(sp)
-; RV32ZDINX-NEXT: sw a1, 12(sp)
-; RV32ZDINX-NEXT: lw a0, 8(sp)
-; RV32ZDINX-NEXT: lw a1, 12(sp)
-; RV32ZDINX-NEXT: addi sp, sp, 16
; RV32ZDINX-NEXT: ret
;
; RV64ZDINX-LABEL: select_icmp_slt_one:
@@ -488,15 +371,8 @@ define double @select_icmp_sgt_zero(i32 signext %a) {
;
; RV32ZDINX-LABEL: select_icmp_sgt_zero:
; RV32ZDINX: # %bb.0:
-; RV32ZDINX-NEXT: addi sp, sp, -16
-; RV32ZDINX-NEXT: .cfi_def_cfa_offset 16
; RV32ZDINX-NEXT: slti a0, a0, 1
; RV32ZDINX-NEXT: fcvt.d.w a0, a0
-; RV32ZDINX-NEXT: sw a0, 8(sp)
-; RV32ZDINX-NEXT: sw a1, 12(sp)
-; RV32ZDINX-NEXT: lw a0, 8(sp)
-; RV32ZDINX-NEXT: lw a1, 12(sp)
-; RV32ZDINX-NEXT: addi sp, sp, 16
; RV32ZDINX-NEXT: ret
;
; RV64ZDINX-LABEL: select_icmp_sgt_zero:
diff --git a/llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll b/llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
index aa88a365431a57..4ae912a34d337c 100644
--- a/llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
+++ b/llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
@@ -62,40 +62,28 @@ define double @func(double %d, i32 %n) nounwind {
;
; RV32IZFINXZDINX-LABEL: func:
; RV32IZFINXZDINX: # %bb.0: # %entry
-; RV32IZFINXZDINX-NEXT: addi sp, sp, -32
-; RV32IZFINXZDINX-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw s0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw s1, 12(sp)
+; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
+; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT: mv s1, a1
+; RV32IZFINXZDINX-NEXT: mv s0, a0
; RV32IZFINXZDINX-NEXT: beqz a2, .LBB0_2
; RV32IZFINXZDINX-NEXT: # %bb.1: # %if.else
; RV32IZFINXZDINX-NEXT: addi a2, a2, -1
-; RV32IZFINXZDINX-NEXT: sw s0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw s1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
+; RV32IZFINXZDINX-NEXT: mv a0, s0
+; RV32IZFINXZDINX-NEXT: mv a1, s1
; RV32IZFINXZDINX-NEXT: call func
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, s0
-; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: j .LBB0_3
; RV32IZFINXZDINX-NEXT: .LBB0_2: # %return
-; RV32IZFINXZDINX-NEXT: sw s0, 8(sp)
-; RV32IZFINXZDINX-NEXT: sw s1, 12(sp)
+; RV32IZFINXZDINX-NEXT: mv a0, s0
+; RV32IZFINXZDINX-NEXT: mv a1, s1
; RV32IZFINXZDINX-NEXT: .LBB0_3: # %return
-; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
-; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
-; RV32IZFINXZDINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT: addi sp, sp, 32
+; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZFINXZDINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: func:
diff --git a/llvm/test/CodeGen/RISCV/fastcc-without-f-reg.ll b/llvm/test/CodeGen/RISCV/fastcc-without-f-reg.ll
index fb0b34cf796be0..a44d31dff09ccb 100644
--- a/llvm/test/CodeGen/RISCV/fastcc-without-f-reg.ll
+++ b/llvm/test/CodeGen/RISCV/fastcc-without-f-reg.ll
@@ -160,17 +160,13 @@ define double @caller_double(double %x) nounwind {
;
; ZDINX32-LABEL: caller_double:
; ZDINX32: # %bb.0: # %entry
-; ZDINX32-NEXT: addi sp, sp, -32
-; ZDINX32-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; ZDINX32-NEXT: sw a0, 16(sp)
-; ZDINX32-NEXT: sw a1, 20(sp)
-; ZDINX32-NEXT: lw a0, 16(sp)
-; ZDINX32-NEXT: lw a1, 20(sp)
+; ZDINX32-NEXT: addi sp, sp, -16
+; ZDINX32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; ZDINX32-NEXT: sw a0, 0(sp)
; ZDINX32-NEXT: sw a1, 4(sp)
; ZDINX32-NEXT: call d
-; ZDINX32-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; ZDINX32-NEXT: addi sp, sp, 32
+; ZDINX32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; ZDINX32-NEXT: addi sp, sp, 16
; ZDINX32-NEXT: ret
;
; ZDINX64-LABEL: caller_double:
@@ -200,14 +196,8 @@ define internal fastcc double @d(double %x) nounwind {
;
; ZDINX32-LABEL: d:
; ZDINX32: # %bb.0: # %entry
-; ZDINX32-NEXT: addi sp, sp, -16
-; ZDINX32-NEXT: lw a0, 16(sp)
-; ZDINX32-NEXT: lw a1, 20(sp)
-; ZDINX32-NEXT: sw a0, 8(sp)
-; ZDINX32-NEXT: sw a1, 12(sp)
-; ZDINX32-NEXT: lw a0, 8(sp)
-; ZDINX32-NEXT: lw a1, 12(sp)
-; ZDINX32-NEXT: addi sp, sp, 16
+; ZDINX32-NEXT: lw a0, 0(sp)
+; ZDINX32-NEXT: lw a1, 4(sp)
; ZDINX32-NEXT: ret
;
; ZDINX64-LABEL: d:
@@ -1360,14 +1350,8 @@ define fastcc double @callee_double_32(<32 x double> %A) nounwind {
;
; ZDINX32-LABEL: callee_double_32:
; ZDINX32: # %bb.0:
-; ZDINX32-NEXT: addi sp, sp, -16
-; ZDINX32-NEXT: lw a0, 16(sp)
-; ZDINX32-NEXT: lw a1, 20(sp)
-; ZDINX32-NEXT: sw a0, 8(sp)
-; ZDINX32-NEXT: sw a1, 12(sp)
-; ZDINX32-NEXT: lw a0, 8(sp)
-; ZDINX32-NEXT: lw a1, 12(sp)
-; ZDINX32-NEXT: addi sp, sp, 16
+; ZDINX32-NEXT: lw a0, 0(sp)
+; ZDINX32-NEXT: lw a1, 4(sp)
; ZDINX32-NEXT: ret
;
; ZDINX64-LABEL: callee_double_32:
diff --git a/llvm/test/CodeGen/RISCV/half-convert-strict.ll b/llvm/test/CodeGen/RISCV/half-convert-strict.ll
index f03a020762bb3c..677aa9263ea615 100644
--- a/llvm/test/CodeGen/RISCV/half-convert-strict.ll
+++ b/llvm/test/CodeGen/RISCV/half-convert-strict.ll
@@ -1745,13 +1745,7 @@ define half @fcvt_h_d(double %a) nounwind strictfp {
;
; RV32IZDINXZHINX-LABEL: fcvt_h_d:
; RV32IZDINXZHINX: # %bb.0:
-; RV32IZDINXZHINX-NEXT: addi sp, sp, -16
-; RV32IZDINXZHINX-NEXT: sw a0, 8(sp)
-; RV32IZDINXZHINX-NEXT: sw a1, 12(sp)
-; RV32IZDINXZHINX-NEXT: lw a0, 8(sp)
-; RV32IZDINXZHINX-NEXT: lw a1, 12(sp)
; RV32IZDINXZHINX-NEXT: fcvt.h.d a0, a0
-; RV32IZDINXZHINX-NEXT: addi sp, sp, 16
; RV32IZDINXZHINX-NEXT: ret
;
; RV64IZDINXZHINX-LABEL: fcvt_h_d:
@@ -1807,13 +1801,7 @@ define half @fcvt_h_d(double %a) nounwind strictfp {
;
; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_d:
; CHECK32-IZDINXZHINXMIN: # %bb.0:
-; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, -16
-; CHECK32-IZDINXZHINXMIN-NEXT: sw a0, 8(sp)
-; CHECK32-IZDINXZHINXMIN-NEXT: sw a1, 12(sp)
-; CHECK32-IZDINXZHINXMIN-NEXT: lw a0, 8(sp)
-; CHECK32-IZDINXZHINXMIN-NEXT: lw a1, 12(sp)
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.h.d a0, a0
-; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, 16
; CHECK32-IZDINXZHINXMIN-NEXT: ret
;
; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_d:
@@ -1878,13 +1866,7 @@ define double @fcvt_d_h(half %a) nounwind strictfp {
;
; RV32IZDINXZHINX-LABEL: fcvt_d_h:
; RV32IZDINXZHINX: # %bb.0:
-; RV32IZDINXZHINX-NEXT: addi sp, sp, -16
; RV32IZDINXZHINX-NEXT: fcvt.d.h a0, a0
-; RV32IZDINXZHINX-NEXT: sw a0, 8(sp)
-; RV32IZDINXZHINX-NEXT: sw a1, 12(sp)
-; RV32IZDINXZHINX-NEXT: lw a0, 8(sp)
-; RV32IZDINXZHINX-NEXT: lw a1, 12(sp)
-; RV32IZDINXZHINX-NEXT: addi sp, sp, 16
; RV32IZDINXZHINX-NEXT: ret
;
; RV64IZDINXZHINX-LABEL: fcvt_d_h:
@@ -1944,13 +1926,7 @@ define double @fcvt_d_h(half %a) nounwind strictfp {
;
; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_d_h:
; CHECK32-IZDINXZHINXMIN: # %bb.0:
-; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, -16
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.d.h a0, a0
-; CHECK32-IZDINXZHINXMIN-NEXT: sw a0, 8(sp)
-; CHECK32-IZDINXZHINXMIN-NEXT: sw a1, 12(sp)
-; CHECK32-IZDINXZHINXMIN-NEXT: lw a0, 8(sp)
-; CHECK32-IZDINXZHINXMIN-NEXT: lw a1, 12(sp)
-; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, 16
; CHECK32-IZDINXZHINXMIN-NEXT: ret
;
; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_d_h:
diff --git a/llvm/test/CodeGen/RISCV/half-convert.ll b/llvm/test/CodeGen/RISCV/half-convert.ll
index 28ac6e272e11df..bc63b396195244 100644
--- a/llvm/test/CodeGen/RISCV/half-convert.ll
+++ b/llvm/test/CodeGen/RISCV/half-convert.ll
@@ -5275,21 +5275,10 @@ define half @fcvt_h_d(double %a) nounwind {
; RV64IZHINX-NEXT: addi sp, sp, 16
; RV64IZHINX-NEXT: ret
;
-; RV32IZDINXZHINX-LABEL: fcvt_h_d:
-; RV32IZDINXZHINX: # %bb.0:
-; RV32IZDINXZHINX-NEXT: addi sp, sp, -16
-; RV32IZDINXZHINX-NEXT: sw a0, 8(sp)
-; RV32IZDINXZHINX-NEXT: sw a1, 12(sp)
-; RV32IZDINXZHINX-NEXT: lw a0, 8(sp)
-; RV32IZDINXZHINX-NEXT: lw a1, 12(sp)
-; RV32IZDINXZHINX-NEXT: fcvt.h.d a0, a0
-; RV32IZDINXZHINX-NEXT: addi sp, sp, 16
-; RV32IZDINXZHINX-NEXT: ret
-;
-; RV64IZDINXZHINX-LABEL: fcvt_h_d:
-; RV64IZDINXZHINX: # %bb.0:
-; RV64IZDINXZHINX-NEXT: fcvt.h.d a0, a0
-; RV64IZDINXZHINX-NEXT: ret
+; CHECKIZDINXZHINX-LABEL: fcvt_h_d:
+; CHECKIZDINXZHINX: # %bb.0:
+; CHECKIZDINXZHINX-NEXT: fcvt.h.d a0, a0
+; CHECKIZDINXZHINX-NEXT: ret
;
; RV32I-LABEL: fcvt_h_d:
; RV32I: # %bb.0:
@@ -5405,13 +5394,7 @@ define half @fcvt_h_d(double %a) nounwind {
;
; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_d:
; CHECK32-IZDINXZHINXMIN: # %bb.0:
-; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, -16
-; CHECK32-IZDINXZHINXMIN-NEXT: sw a0, 8(sp)
-; CHECK32-IZDINXZHINXMIN-NEXT: sw a1, 12(sp)
-; CHECK32-IZDINXZHINXMIN-NEXT: lw a0, 8(sp)
-; CHECK32-IZDINXZHINXMIN-NEXT: lw a1, 12(sp)
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.h.d a0, a0
-; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, 16
; CHECK32-IZDINXZHINXMIN-NEXT: ret
;
; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_d:
@@ -5473,21 +5456,10 @@ define double @fcvt_d_h(half %a) nounwind {
; RV64IZHINX-NEXT: addi sp, sp, 16
; RV64IZHINX-NEXT: ret
;
-; RV32IZDINXZHINX-LABEL: fcvt_d_h:
-; RV32IZDINXZHINX: # %bb.0:
-; RV32IZDINXZHINX-NEXT: addi sp, sp, -16
-; RV32IZDINXZHINX-NEXT: fcvt.d.h a0, a0
-; RV32IZDINXZHINX-NEXT: sw a0, 8(sp)
-; RV32IZDINXZHINX-NEXT: sw a1, 12(sp)
-; RV32IZDINXZHINX-NEXT: lw a0, 8(sp)
-; RV32IZDINXZHINX-NEXT: lw a1, 12(sp)
-; RV32IZDINXZHINX-NEXT: addi sp, sp, 16
-; RV32IZDINXZHINX-NEXT: ret
-;
-; RV64IZDINXZHINX-LABEL: fcvt_d_h:
-; RV64IZDINXZHINX: # %bb.0:
-; RV64IZDINXZHINX-NEXT: fcvt.d.h a0, a0
-; RV64IZDINXZHINX-NEXT: ret
+; CHECKIZDINXZHINX-LABEL: fcvt_d_h:
+; CHECKIZDINXZHINX: # %bb.0:
+; CHECKIZDINXZHINX-NEXT: fcvt.d.h a0, a0
+; CHECKIZDINXZHINX-NEXT: ret
;
; RV32I-LABEL: fcvt_d_h:
; RV32I: # %bb.0:
@@ -5607,13 +5579,7 @@ define double @fcvt_d_h(half %a) nounwind {
;
; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_d_h:
; CHECK32-IZDINXZHINXMIN: # %bb.0:
-; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, -16
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.d.h a0, a0
-; CHECK32-IZDINXZHINXMIN-NEXT: sw a0, 8(sp)
-; CHECK32-IZDINXZHINXMIN-NEXT: sw a1, 12(sp)
-; CHECK32-IZDINXZHINXMIN-NEXT: lw a0, 8(sp)
-; CHECK32-IZDINXZHINXMIN-NEXT: lw a1, 12(sp)
-; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, 16
; CHECK32-IZDINXZHINXMIN-NEXT: ret
;
; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_d_h:
diff --git a/llvm/test/CodeGen/RISCV/pr64645.ll b/llvm/test/CodeGen/RISCV/pr64645.ll
index 44dce5aabd2242..f6d46516a3c005 100644
--- a/llvm/test/CodeGen/RISCV/pr64645.ll
+++ b/llvm/test/CodeGen/RISCV/pr64645.ll
@@ -5,34 +5,8 @@
define <2 x double> @v2f64(<2 x double> %x, <2 x double> %y) nounwind {
; CHECK-LABEL: v2f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a4, 8(sp)
-; CHECK-NEXT: sw a5, 12(sp)
-; CHECK-NEXT: lw a4, 8(sp)
-; CHECK-NEXT: lw a5, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: lw a0, 8(sp)
-; CHECK-NEXT: lw a1, 12(sp)
-; CHECK-NEXT: sw a6, 8(sp)
-; CHECK-NEXT: sw a7, 12(sp)
-; CHECK-NEXT: lw a6, 8(sp)
-; CHECK-NEXT: lw a7, 12(sp)
-; CHECK-NEXT: sw a2, 8(sp)
-; CHECK-NEXT: sw a3, 12(sp)
-; CHECK-NEXT: lw a2, 8(sp)
-; CHECK-NEXT: lw a3, 12(sp)
; CHECK-NEXT: fadd.d a2, a2, a6
; CHECK-NEXT: fadd.d a0, a0, a4
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: lw a0, 8(sp)
-; CHECK-NEXT: lw a1, 12(sp)
-; CHECK-NEXT: sw a2, 8(sp)
-; CHECK-NEXT: sw a3, 12(sp)
-; CHECK-NEXT: lw a2, 8(sp)
-; CHECK-NEXT: lw a3, 12(sp)
-; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%1 = fadd <2 x double> %x, %y
ret <2 x double> %1
diff --git a/llvm/test/CodeGen/RISCV/zdinx-asm-constraint.ll b/llvm/test/CodeGen/RISCV/zdinx-asm-constraint.ll
index 63c46ca4eafce8..95695aa697764a 100644
--- a/llvm/test/CodeGen/RISCV/zdinx-asm-constraint.ll
+++ b/llvm/test/CodeGen/RISCV/zdinx-asm-constraint.ll
@@ -4,21 +4,15 @@
define dso_local void @zdinx_asm(ptr nocapture noundef writeonly %a, double noundef %b, double noundef %c) nounwind {
; CHECK-LABEL: zdinx_asm:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 8(sp)
-; CHECK-NEXT: sw a2, 12(sp)
-; CHECK-NEXT: lw a6, 8(sp)
-; CHECK-NEXT: lw a7, 12(sp)
-; CHECK-NEXT: sw a3, 8(sp)
-; CHECK-NEXT: sw a4, 12(sp)
-; CHECK-NEXT: lw a2, 8(sp)
-; CHECK-NEXT: lw a3, 12(sp)
+; CHECK-NEXT: mv a5, a4
+; CHECK-NEXT: mv a7, a2
+; CHECK-NEXT: mv a4, a3
+; CHECK-NEXT: mv a6, a1
; CHECK-NEXT: #APP
-; CHECK-NEXT: fsgnjx.d a2, a6, a2
+; CHECK-NEXT: fsgnjx.d a2, a6, a4
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: sw a2, 8(a0)
; CHECK-NEXT: sw a3, 12(a0)
-; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
%arrayidx = getelementptr inbounds double, ptr %a, i32 1
diff --git a/llvm/test/CodeGen/RISCV/zdinx-boundary-check.ll b/llvm/test/CodeGen/RISCV/zdinx-boundary-check.ll
index 3eeb704f80ebac..f56d47716bd781 100644
--- a/llvm/test/CodeGen/RISCV/zdinx-boundary-check.ll
+++ b/llvm/test/CodeGen/RISCV/zdinx-boundary-check.ll
@@ -7,15 +7,11 @@
define void @foo(ptr nocapture %p, double %d) nounwind {
; RV32ZDINX-LABEL: foo:
; RV32ZDINX: # %bb.0: # %entry
-; RV32ZDINX-NEXT: addi sp, sp, -16
-; RV32ZDINX-NEXT: sw a1, 8(sp)
-; RV32ZDINX-NEXT: sw a2, 12(sp)
-; RV32ZDINX-NEXT: lw a2, 8(sp)
-; RV32ZDINX-NEXT: lw a3, 12(sp)
+; RV32ZDINX-NEXT: mv a3, a2
; RV32ZDINX-NEXT: addi a0, a0, 2047
+; RV32ZDINX-NEXT: mv a2, a1
; RV32ZDINX-NEXT: sw a2, -3(a0)
; RV32ZDINX-NEXT: sw a3, 1(a0)
-; RV32ZDINX-NEXT: addi sp, sp, 16
; RV32ZDINX-NEXT: ret
;
; RV64ZDINX-LABEL: foo:
@@ -31,16 +27,12 @@ entry:
define void @foo2(ptr nocapture %p, double %d) nounwind {
; RV32ZDINX-LABEL: foo2:
; RV32ZDINX: # %bb.0: # %entry
-; RV32ZDINX-NEXT: addi sp, sp, -16
-; RV32ZDINX-NEXT: sw a1, 8(sp)
-; RV32ZDINX-NEXT: sw a2, 12(sp)
-; RV32ZDINX-NEXT: lw a2, 8(sp)
-; RV32ZDINX-NEXT: lw a3, 12(sp)
+; RV32ZDINX-NEXT: mv a3, a2
+; RV32ZDINX-NEXT: mv a2, a1
; RV32ZDINX-NEXT: fadd.d a2, a2, a2
; RV32ZDINX-NEXT: addi a0, a0, 2047
; RV32ZDINX-NEXT: sw a2, -3(a0)
; RV32ZDINX-NEXT: sw a3, 1(a0)
-; RV32ZDINX-NEXT: addi sp, sp, 16
; RV32ZDINX-NEXT: ret
;
; RV64ZDINX-LABEL: foo2:
@@ -117,15 +109,11 @@ entry:
define void @foo5(ptr nocapture %p, double %d) nounwind {
; RV32ZDINX-LABEL: foo5:
; RV32ZDINX: # %bb.0: # %entry
-; RV32ZDINX-NEXT: addi sp, sp, -16
-; RV32ZDINX-NEXT: sw a1, 8(sp)
-; RV32ZDINX-NEXT: sw a2, 12(sp)
-; RV32ZDINX-NEXT: lw a2, 8(sp)
-; RV32ZDINX-NEXT: lw a3, 12(sp)
+; RV32ZDINX-NEXT: mv a3, a2
; RV32ZDINX-NEXT: addi a0, a0, -2048
+; RV32ZDINX-NEXT: mv a2, a1
; RV32ZDINX-NEXT: sw a2, -1(a0)
; RV32ZDINX-NEXT: sw a3, 3(a0)
-; RV32ZDINX-NEXT: addi sp, sp, 16
; RV32ZDINX-NEXT: ret
;
; RV64ZDINX-LABEL: foo5:
@@ -142,19 +130,15 @@ entry:
define void @foo6(ptr %p, double %d) nounwind {
; RV32ZDINX-LABEL: foo6:
; RV32ZDINX: # %bb.0: # %entry
-; RV32ZDINX-NEXT: addi sp, sp, -16
-; RV32ZDINX-NEXT: sw a1, 8(sp)
-; RV32ZDINX-NEXT: sw a2, 12(sp)
-; RV32ZDINX-NEXT: lw a2, 8(sp)
-; RV32ZDINX-NEXT: lw a3, 12(sp)
-; RV32ZDINX-NEXT: lui a1, %hi(.LCPI5_0)
-; RV32ZDINX-NEXT: lw a4, %lo(.LCPI5_0)(a1)
-; RV32ZDINX-NEXT: lw a5, %lo(.LCPI5_0+4)(a1)
+; RV32ZDINX-NEXT: lui a3, %hi(.LCPI5_0)
+; RV32ZDINX-NEXT: lw a4, %lo(.LCPI5_0)(a3)
+; RV32ZDINX-NEXT: lw a5, %lo(.LCPI5_0+4)(a3)
+; RV32ZDINX-NEXT: mv a3, a2
+; RV32ZDINX-NEXT: mv a2, a1
; RV32ZDINX-NEXT: fadd.d a2, a2, a4
; RV32ZDINX-NEXT: addi a0, a0, 2047
; RV32ZDINX-NEXT: sw a2, -3(a0)
; RV32ZDINX-NEXT: sw a3, 1(a0)
-; RV32ZDINX-NEXT: addi sp, sp, 16
; RV32ZDINX-NEXT: ret
;
; RV64ZDINX-LABEL: foo6:
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