[llvm] [MIPS] Fix the opcode of max.fmt and mina.fmt and make them matchable by ISel (PR #85609)
Cinhi Young via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 20 03:09:02 PDT 2024
https://github.com/Cyanoxygen updated https://github.com/llvm/llvm-project/pull/85609
>From 70b5b14bfd15da317f8df078a7f859c76251c235 Mon Sep 17 00:00:00 2001
From: Cyan <cyanoxygen at aosc.io>
Date: Wed, 13 Mar 2024 17:03:35 +0800
Subject: [PATCH 1/3] [MIPS] Fix the func opcode for mina.fmt and max.fmt
- The opcode of the mina.fmt and max.fmt is documented wrong, the
object code compiled from the same assembly with LLVM behaves
differently than one compiled with GCC and Binutils.
- Modify the opcodes to match Binutils. The actual opcodes are as follows:
{5,3}| bits {2,0} of func
| ... | 100 | 101 | 110 | 111
-----+-----+-----+-----+-----+-----
010 | ... | min | mina| max | maxa
---
llvm/lib/Target/Mips/Mips32r6InstrInfo.td | 24 +++++++++++++++++++----
1 file changed, 20 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
index 9c29acbd0d8a88..f609305bfee429 100644
--- a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
+++ b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
@@ -153,15 +153,15 @@ class SELNEZ_ENC : SPECIAL_3R_FM<0b00000, 0b110111>;
class LWPC_ENC : PCREL19_FM<OPCODE2_LWPC>;
-class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>;
-class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>;
+class MAX_S_ENC : COP1_3R_FM<0b011110, FIELD_FMT_S>;
+class MAX_D_ENC : COP1_3R_FM<0b011110, FIELD_FMT_D>;
class MIN_S_ENC : COP1_3R_FM<0b011100, FIELD_FMT_S>;
class MIN_D_ENC : COP1_3R_FM<0b011100, FIELD_FMT_D>;
class MAXA_S_ENC : COP1_3R_FM<0b011111, FIELD_FMT_S>;
class MAXA_D_ENC : COP1_3R_FM<0b011111, FIELD_FMT_D>;
-class MINA_S_ENC : COP1_3R_FM<0b011110, FIELD_FMT_S>;
-class MINA_D_ENC : COP1_3R_FM<0b011110, FIELD_FMT_D>;
+class MINA_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>;
+class MINA_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>;
class SELEQZ_S_ENC : COP1_3R_FM<0b010100, FIELD_FMT_S>;
class SELEQZ_D_ENC : COP1_3R_FM<0b010100, FIELD_FMT_D>;
@@ -1117,6 +1117,22 @@ def : MipsPat<(select i32:$cond, immz, i32:$f),
ISA_MIPS32R6;
}
+// llvm.fmin/fmax operations.
+let AdditionalPredicates = [NotInMicroMips] in {
+ def : MipsPat<(fmaxnum f32:$lhs, f32:$rhs),
+ (MAX_S f32:$lhs, f32:$rhs)>,
+ ISA_MIPS32R6;
+ def : MipsPat<(fmaxnum f64:$lhs, f64:$rhs),
+ (MAX_D f64:$lhs, f64:$rhs)>,
+ ISA_MIPS32R6;
+ def : MipsPat<(fminnum f32:$lhs, f32:$rhs),
+ (MIN_S f32:$lhs, f32:$rhs)>,
+ ISA_MIPS32R6;
+ def : MipsPat<(fminnum f64:$lhs, f64:$rhs),
+ (MIN_D f64:$lhs, f64:$rhs)>,
+ ISA_MIPS32R6;
+}
+
// Pseudo instructions
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
hasExtraSrcRegAllocReq = 1, isCTI = 1, Defs = [AT], hasPostISelHook = 1 in {
>From 5d109fb38c5b5963ba86cd3472c61a38039f46a7 Mon Sep 17 00:00:00 2001
From: Cyan <cyanoxygen at aosc.io>
Date: Mon, 18 Mar 2024 15:29:11 +0800
Subject: [PATCH 2/3] [MIPS] match llvm.{min,max}num with {min,max}.fmt for R6
- The behavior is similar to UCOMISD on x86, which is also used to
compare two fp values, specifically on handling of NaNs.
---
llvm/lib/Target/Mips/MipsISelLowering.cpp | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index 0a0d40751fcf05..add2ec6fc64a2f 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -358,6 +358,15 @@ MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
+ // Lower fmin and fmax operations for MIPS R6.
+ // Instructions are defined but never used.
+ if (Subtarget.hasMips32r6()) {
+ setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
+ setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
+ setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
+ setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
+ }
+
if (Subtarget.isGP64bit()) {
setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
>From ff9b37e3fa87faec226153e7bd06e22029c6607e Mon Sep 17 00:00:00 2001
From: Cyan <cyanoxygen at aosc.io>
Date: Wed, 20 Mar 2024 18:03:32 +0800
Subject: [PATCH 3/3] [MIPS] Fix tests after the opcode correction
- Also create MC tests for fminnum and fmaxnum on R6, since they are now
matchable by ISel directly.
---
llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll | 487 +++++++++++-------
.../Mips/mips32r6/valid-mips32r6-el.txt | 8 +-
.../Mips/mips32r6/valid-mips32r6.txt | 8 +-
.../Mips/mips64r6/valid-mips64r6-el.txt | 8 +-
.../Mips/mips64r6/valid-mips64r6.txt | 8 +-
llvm/test/MC/Mips/mips32r6/valid.s | 8 +-
llvm/test/MC/Mips/mips64r6/valid.s | 8 +-
7 files changed, 325 insertions(+), 210 deletions(-)
diff --git a/llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll b/llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll
index 45c7ab980edd64..fe68bee408fc89 100644
--- a/llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll
+++ b/llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll
@@ -2365,101 +2365,159 @@ entry:
declare float @llvm.minnum.f32(float %Val, float %b)
define void @fminnum(float %b) {
-; MIPS32-LABEL: fminnum:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: lui $2, %hi(_gp_disp)
-; MIPS32-NEXT: addiu $2, $2, %lo(_gp_disp)
-; MIPS32-NEXT: addiu $sp, $sp, -24
-; MIPS32-NEXT: .cfi_def_cfa_offset 24
-; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
-; MIPS32-NEXT: sw $16, 16($sp) # 4-byte Folded Spill
-; MIPS32-NEXT: .cfi_offset 31, -4
-; MIPS32-NEXT: .cfi_offset 16, -8
-; MIPS32-NEXT: addu $gp, $2, $25
-; MIPS32-NEXT: mov.s $f14, $f12
-; MIPS32-NEXT: lw $16, %got(g)($gp)
-; MIPS32-NEXT: lh $1, 0($16)
-; MIPS32-NEXT: fill.h $w0, $1
-; MIPS32-NEXT: fexupr.w $w0, $w0
-; MIPS32-NEXT: copy_s.w $1, $w0[0]
-; MIPS32-NEXT: lw $25, %call16(fminf)($gp)
-; MIPS32-NEXT: jalr $25
-; MIPS32-NEXT: mtc1 $1, $f12
-; MIPS32-NEXT: mfc1 $1, $f0
-; MIPS32-NEXT: fill.w $w0, $1
-; MIPS32-NEXT: fexdo.h $w0, $w0, $w0
-; MIPS32-NEXT: copy_u.h $1, $w0[0]
-; MIPS32-NEXT: sh $1, 0($16)
-; MIPS32-NEXT: lw $16, 16($sp) # 4-byte Folded Reload
-; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: addiu $sp, $sp, 24
+; MIPS32-O32-LABEL: fminnum:
+; MIPS32-O32: # %bb.0: # %entry
+; MIPS32-O32-NEXT: lui $2, %hi(_gp_disp)
+; MIPS32-O32-NEXT: addiu $2, $2, %lo(_gp_disp)
+; MIPS32-O32-NEXT: addiu $sp, $sp, -24
+; MIPS32-O32-NEXT: .cfi_def_cfa_offset 24
+; MIPS32-O32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
+; MIPS32-O32-NEXT: sw $16, 16($sp) # 4-byte Folded Spill
+; MIPS32-O32-NEXT: .cfi_offset 31, -4
+; MIPS32-O32-NEXT: .cfi_offset 16, -8
+; MIPS32-O32-NEXT: addu $gp, $2, $25
+; MIPS32-O32-NEXT: mov.s $f14, $f12
+; MIPS32-O32-NEXT: lw $16, %got(g)($gp)
+; MIPS32-O32-NEXT: lh $1, 0($16)
+; MIPS32-O32-NEXT: fill.h $w0, $1
+; MIPS32-O32-NEXT: fexupr.w $w0, $w0
+; MIPS32-O32-NEXT: copy_s.w $1, $w0[0]
+; MIPS32-O32-NEXT: lw $25, %call16(fminf)($gp)
+; MIPS32-O32-NEXT: jalr $25
+; MIPS32-O32-NEXT: mtc1 $1, $f12
+; MIPS32-O32-NEXT: mfc1 $1, $f0
+; MIPS32-O32-NEXT: fill.w $w0, $1
+; MIPS32-O32-NEXT: fexdo.h $w0, $w0, $w0
+; MIPS32-O32-NEXT: copy_u.h $1, $w0[0]
+; MIPS32-O32-NEXT: sh $1, 0($16)
+; MIPS32-O32-NEXT: lw $16, 16($sp) # 4-byte Folded Reload
+; MIPS32-O32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
+; MIPS32-O32-NEXT: jr $ra
+; MIPS32-O32-NEXT: addiu $sp, $sp, 24
;
-; MIPS64-N32-LABEL: fminnum:
-; MIPS64-N32: # %bb.0: # %entry
-; MIPS64-N32-NEXT: addiu $sp, $sp, -32
-; MIPS64-N32-NEXT: .cfi_def_cfa_offset 32
-; MIPS64-N32-NEXT: sd $ra, 24($sp) # 8-byte Folded Spill
-; MIPS64-N32-NEXT: sd $gp, 16($sp) # 8-byte Folded Spill
-; MIPS64-N32-NEXT: sd $16, 8($sp) # 8-byte Folded Spill
-; MIPS64-N32-NEXT: .cfi_offset 31, -8
-; MIPS64-N32-NEXT: .cfi_offset 28, -16
-; MIPS64-N32-NEXT: .cfi_offset 16, -24
-; MIPS64-N32-NEXT: lui $1, %hi(%neg(%gp_rel(fminnum)))
-; MIPS64-N32-NEXT: addu $1, $1, $25
-; MIPS64-N32-NEXT: addiu $gp, $1, %lo(%neg(%gp_rel(fminnum)))
-; MIPS64-N32-NEXT: mov.s $f13, $f12
-; MIPS64-N32-NEXT: lw $16, %got_disp(g)($gp)
-; MIPS64-N32-NEXT: lh $1, 0($16)
-; MIPS64-N32-NEXT: fill.h $w0, $1
-; MIPS64-N32-NEXT: fexupr.w $w0, $w0
-; MIPS64-N32-NEXT: copy_s.w $1, $w0[0]
-; MIPS64-N32-NEXT: lw $25, %call16(fminf)($gp)
-; MIPS64-N32-NEXT: jalr $25
-; MIPS64-N32-NEXT: mtc1 $1, $f12
-; MIPS64-N32-NEXT: mfc1 $1, $f0
-; MIPS64-N32-NEXT: fill.w $w0, $1
-; MIPS64-N32-NEXT: fexdo.h $w0, $w0, $w0
-; MIPS64-N32-NEXT: copy_u.h $1, $w0[0]
-; MIPS64-N32-NEXT: sh $1, 0($16)
-; MIPS64-N32-NEXT: ld $16, 8($sp) # 8-byte Folded Reload
-; MIPS64-N32-NEXT: ld $gp, 16($sp) # 8-byte Folded Reload
-; MIPS64-N32-NEXT: ld $ra, 24($sp) # 8-byte Folded Reload
-; MIPS64-N32-NEXT: jr $ra
-; MIPS64-N32-NEXT: addiu $sp, $sp, 32
+; MIPS64R5-N32-LABEL: fminnum:
+; MIPS64R5-N32: # %bb.0: # %entry
+; MIPS64R5-N32-NEXT: addiu $sp, $sp, -32
+; MIPS64R5-N32-NEXT: .cfi_def_cfa_offset 32
+; MIPS64R5-N32-NEXT: sd $ra, 24($sp) # 8-byte Folded Spill
+; MIPS64R5-N32-NEXT: sd $gp, 16($sp) # 8-byte Folded Spill
+; MIPS64R5-N32-NEXT: sd $16, 8($sp) # 8-byte Folded Spill
+; MIPS64R5-N32-NEXT: .cfi_offset 31, -8
+; MIPS64R5-N32-NEXT: .cfi_offset 28, -16
+; MIPS64R5-N32-NEXT: .cfi_offset 16, -24
+; MIPS64R5-N32-NEXT: lui $1, %hi(%neg(%gp_rel(fminnum)))
+; MIPS64R5-N32-NEXT: addu $1, $1, $25
+; MIPS64R5-N32-NEXT: addiu $gp, $1, %lo(%neg(%gp_rel(fminnum)))
+; MIPS64R5-N32-NEXT: mov.s $f13, $f12
+; MIPS64R5-N32-NEXT: lw $16, %got_disp(g)($gp)
+; MIPS64R5-N32-NEXT: lh $1, 0($16)
+; MIPS64R5-N32-NEXT: fill.h $w0, $1
+; MIPS64R5-N32-NEXT: fexupr.w $w0, $w0
+; MIPS64R5-N32-NEXT: copy_s.w $1, $w0[0]
+; MIPS64R5-N32-NEXT: lw $25, %call16(fminf)($gp)
+; MIPS64R5-N32-NEXT: jalr $25
+; MIPS64R5-N32-NEXT: mtc1 $1, $f12
+; MIPS64R5-N32-NEXT: mfc1 $1, $f0
+; MIPS64R5-N32-NEXT: fill.w $w0, $1
+; MIPS64R5-N32-NEXT: fexdo.h $w0, $w0, $w0
+; MIPS64R5-N32-NEXT: copy_u.h $1, $w0[0]
+; MIPS64R5-N32-NEXT: sh $1, 0($16)
+; MIPS64R5-N32-NEXT: ld $16, 8($sp) # 8-byte Folded Reload
+; MIPS64R5-N32-NEXT: ld $gp, 16($sp) # 8-byte Folded Reload
+; MIPS64R5-N32-NEXT: ld $ra, 24($sp) # 8-byte Folded Reload
+; MIPS64R5-N32-NEXT: jr $ra
+; MIPS64R5-N32-NEXT: addiu $sp, $sp, 32
+;
+; MIPS64R5-N64-LABEL: fminnum:
+; MIPS64R5-N64: # %bb.0: # %entry
+; MIPS64R5-N64-NEXT: daddiu $sp, $sp, -32
+; MIPS64R5-N64-NEXT: .cfi_def_cfa_offset 32
+; MIPS64R5-N64-NEXT: sd $ra, 24($sp) # 8-byte Folded Spill
+; MIPS64R5-N64-NEXT: sd $gp, 16($sp) # 8-byte Folded Spill
+; MIPS64R5-N64-NEXT: sd $16, 8($sp) # 8-byte Folded Spill
+; MIPS64R5-N64-NEXT: .cfi_offset 31, -8
+; MIPS64R5-N64-NEXT: .cfi_offset 28, -16
+; MIPS64R5-N64-NEXT: .cfi_offset 16, -24
+; MIPS64R5-N64-NEXT: lui $1, %hi(%neg(%gp_rel(fminnum)))
+; MIPS64R5-N64-NEXT: daddu $1, $1, $25
+; MIPS64R5-N64-NEXT: daddiu $gp, $1, %lo(%neg(%gp_rel(fminnum)))
+; MIPS64R5-N64-NEXT: mov.s $f13, $f12
+; MIPS64R5-N64-NEXT: ld $16, %got_disp(g)($gp)
+; MIPS64R5-N64-NEXT: lh $1, 0($16)
+; MIPS64R5-N64-NEXT: fill.h $w0, $1
+; MIPS64R5-N64-NEXT: fexupr.w $w0, $w0
+; MIPS64R5-N64-NEXT: copy_s.w $1, $w0[0]
+; MIPS64R5-N64-NEXT: ld $25, %call16(fminf)($gp)
+; MIPS64R5-N64-NEXT: jalr $25
+; MIPS64R5-N64-NEXT: mtc1 $1, $f12
+; MIPS64R5-N64-NEXT: mfc1 $1, $f0
+; MIPS64R5-N64-NEXT: fill.w $w0, $1
+; MIPS64R5-N64-NEXT: fexdo.h $w0, $w0, $w0
+; MIPS64R5-N64-NEXT: copy_u.h $1, $w0[0]
+; MIPS64R5-N64-NEXT: sh $1, 0($16)
+; MIPS64R5-N64-NEXT: ld $16, 8($sp) # 8-byte Folded Reload
+; MIPS64R5-N64-NEXT: ld $gp, 16($sp) # 8-byte Folded Reload
+; MIPS64R5-N64-NEXT: ld $ra, 24($sp) # 8-byte Folded Reload
+; MIPS64R5-N64-NEXT: jr $ra
+; MIPS64R5-N64-NEXT: daddiu $sp, $sp, 32
+;
+; MIPSR6-O32-LABEL: fminnum:
+; MIPSR6-O32: # %bb.0: # %entry
+; MIPSR6-O32-NEXT: lui $2, %hi(_gp_disp)
+; MIPSR6-O32-NEXT: addiu $2, $2, %lo(_gp_disp)
+; MIPSR6-O32-NEXT: addu $1, $2, $25
+; MIPSR6-O32-NEXT: lw $1, %got(g)($1)
+; MIPSR6-O32-NEXT: lh $2, 0($1)
+; MIPSR6-O32-NEXT: fill.h $w0, $2
+; MIPSR6-O32-NEXT: fexupr.w $w0, $w0
+; MIPSR6-O32-NEXT: copy_s.w $2, $w0[0]
+; MIPSR6-O32-NEXT: mtc1 $2, $f0
+; MIPSR6-O32-NEXT: min.s $f0, $f0, $f12
+; MIPSR6-O32-NEXT: mfc1 $2, $f0
+; MIPSR6-O32-NEXT: fill.w $w0, $2
+; MIPSR6-O32-NEXT: fexdo.h $w0, $w0, $w0
+; MIPSR6-O32-NEXT: copy_u.h $2, $w0[0]
+; MIPSR6-O32-NEXT: jr $ra
+; MIPSR6-O32-NEXT: sh $2, 0($1)
+;
+; MIPSR6-N32-LABEL: fminnum:
+; MIPSR6-N32: # %bb.0: # %entry
+; MIPSR6-N32-NEXT: lui $1, %hi(%neg(%gp_rel(fminnum)))
+; MIPSR6-N32-NEXT: addu $1, $1, $25
+; MIPSR6-N32-NEXT: addiu $1, $1, %lo(%neg(%gp_rel(fminnum)))
+; MIPSR6-N32-NEXT: lw $1, %got_disp(g)($1)
+; MIPSR6-N32-NEXT: lh $2, 0($1)
+; MIPSR6-N32-NEXT: fill.h $w0, $2
+; MIPSR6-N32-NEXT: fexupr.w $w0, $w0
+; MIPSR6-N32-NEXT: copy_s.w $2, $w0[0]
+; MIPSR6-N32-NEXT: mtc1 $2, $f0
+; MIPSR6-N32-NEXT: min.s $f0, $f0, $f12
+; MIPSR6-N32-NEXT: mfc1 $2, $f0
+; MIPSR6-N32-NEXT: fill.w $w0, $2
+; MIPSR6-N32-NEXT: fexdo.h $w0, $w0, $w0
+; MIPSR6-N32-NEXT: copy_u.h $2, $w0[0]
+; MIPSR6-N32-NEXT: jr $ra
+; MIPSR6-N32-NEXT: sh $2, 0($1)
+;
+; MIPSR6-N64-LABEL: fminnum:
+; MIPSR6-N64: # %bb.0: # %entry
+; MIPSR6-N64-NEXT: lui $1, %hi(%neg(%gp_rel(fminnum)))
+; MIPSR6-N64-NEXT: daddu $1, $1, $25
+; MIPSR6-N64-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(fminnum)))
+; MIPSR6-N64-NEXT: ld $1, %got_disp(g)($1)
+; MIPSR6-N64-NEXT: lh $2, 0($1)
+; MIPSR6-N64-NEXT: fill.h $w0, $2
+; MIPSR6-N64-NEXT: fexupr.w $w0, $w0
+; MIPSR6-N64-NEXT: copy_s.w $2, $w0[0]
+; MIPSR6-N64-NEXT: mtc1 $2, $f0
+; MIPSR6-N64-NEXT: min.s $f0, $f0, $f12
+; MIPSR6-N64-NEXT: mfc1 $2, $f0
+; MIPSR6-N64-NEXT: fill.w $w0, $2
+; MIPSR6-N64-NEXT: fexdo.h $w0, $w0, $w0
+; MIPSR6-N64-NEXT: copy_u.h $2, $w0[0]
+; MIPSR6-N64-NEXT: jr $ra
+; MIPSR6-N64-NEXT: sh $2, 0($1)
;
-; MIPS64-N64-LABEL: fminnum:
-; MIPS64-N64: # %bb.0: # %entry
-; MIPS64-N64-NEXT: daddiu $sp, $sp, -32
-; MIPS64-N64-NEXT: .cfi_def_cfa_offset 32
-; MIPS64-N64-NEXT: sd $ra, 24($sp) # 8-byte Folded Spill
-; MIPS64-N64-NEXT: sd $gp, 16($sp) # 8-byte Folded Spill
-; MIPS64-N64-NEXT: sd $16, 8($sp) # 8-byte Folded Spill
-; MIPS64-N64-NEXT: .cfi_offset 31, -8
-; MIPS64-N64-NEXT: .cfi_offset 28, -16
-; MIPS64-N64-NEXT: .cfi_offset 16, -24
-; MIPS64-N64-NEXT: lui $1, %hi(%neg(%gp_rel(fminnum)))
-; MIPS64-N64-NEXT: daddu $1, $1, $25
-; MIPS64-N64-NEXT: daddiu $gp, $1, %lo(%neg(%gp_rel(fminnum)))
-; MIPS64-N64-NEXT: mov.s $f13, $f12
-; MIPS64-N64-NEXT: ld $16, %got_disp(g)($gp)
-; MIPS64-N64-NEXT: lh $1, 0($16)
-; MIPS64-N64-NEXT: fill.h $w0, $1
-; MIPS64-N64-NEXT: fexupr.w $w0, $w0
-; MIPS64-N64-NEXT: copy_s.w $1, $w0[0]
-; MIPS64-N64-NEXT: ld $25, %call16(fminf)($gp)
-; MIPS64-N64-NEXT: jalr $25
-; MIPS64-N64-NEXT: mtc1 $1, $f12
-; MIPS64-N64-NEXT: mfc1 $1, $f0
-; MIPS64-N64-NEXT: fill.w $w0, $1
-; MIPS64-N64-NEXT: fexdo.h $w0, $w0, $w0
-; MIPS64-N64-NEXT: copy_u.h $1, $w0[0]
-; MIPS64-N64-NEXT: sh $1, 0($16)
-; MIPS64-N64-NEXT: ld $16, 8($sp) # 8-byte Folded Reload
-; MIPS64-N64-NEXT: ld $gp, 16($sp) # 8-byte Folded Reload
-; MIPS64-N64-NEXT: ld $ra, 24($sp) # 8-byte Folded Reload
-; MIPS64-N64-NEXT: jr $ra
-; MIPS64-N64-NEXT: daddiu $sp, $sp, 32
entry:
%0 = load i16, ptr @g, align 2
%1 = call float @llvm.convert.from.fp16.f32(i16 %0)
@@ -2477,101 +2535,158 @@ entry:
declare float @llvm.maxnum.f32(float %Val, float %b)
define void @fmaxnum(float %b) {
-; MIPS32-LABEL: fmaxnum:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: lui $2, %hi(_gp_disp)
-; MIPS32-NEXT: addiu $2, $2, %lo(_gp_disp)
-; MIPS32-NEXT: addiu $sp, $sp, -24
-; MIPS32-NEXT: .cfi_def_cfa_offset 24
-; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
-; MIPS32-NEXT: sw $16, 16($sp) # 4-byte Folded Spill
-; MIPS32-NEXT: .cfi_offset 31, -4
-; MIPS32-NEXT: .cfi_offset 16, -8
-; MIPS32-NEXT: addu $gp, $2, $25
-; MIPS32-NEXT: mov.s $f14, $f12
-; MIPS32-NEXT: lw $16, %got(g)($gp)
-; MIPS32-NEXT: lh $1, 0($16)
-; MIPS32-NEXT: fill.h $w0, $1
-; MIPS32-NEXT: fexupr.w $w0, $w0
-; MIPS32-NEXT: copy_s.w $1, $w0[0]
-; MIPS32-NEXT: lw $25, %call16(fmaxf)($gp)
-; MIPS32-NEXT: jalr $25
-; MIPS32-NEXT: mtc1 $1, $f12
-; MIPS32-NEXT: mfc1 $1, $f0
-; MIPS32-NEXT: fill.w $w0, $1
-; MIPS32-NEXT: fexdo.h $w0, $w0, $w0
-; MIPS32-NEXT: copy_u.h $1, $w0[0]
-; MIPS32-NEXT: sh $1, 0($16)
-; MIPS32-NEXT: lw $16, 16($sp) # 4-byte Folded Reload
-; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: addiu $sp, $sp, 24
+; MIPS32-O32-LABEL: fmaxnum:
+; MIPS32-O32: # %bb.0: # %entry
+; MIPS32-O32-NEXT: lui $2, %hi(_gp_disp)
+; MIPS32-O32-NEXT: addiu $2, $2, %lo(_gp_disp)
+; MIPS32-O32-NEXT: addiu $sp, $sp, -24
+; MIPS32-O32-NEXT: .cfi_def_cfa_offset 24
+; MIPS32-O32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
+; MIPS32-O32-NEXT: sw $16, 16($sp) # 4-byte Folded Spill
+; MIPS32-O32-NEXT: .cfi_offset 31, -4
+; MIPS32-O32-NEXT: .cfi_offset 16, -8
+; MIPS32-O32-NEXT: addu $gp, $2, $25
+; MIPS32-O32-NEXT: mov.s $f14, $f12
+; MIPS32-O32-NEXT: lw $16, %got(g)($gp)
+; MIPS32-O32-NEXT: lh $1, 0($16)
+; MIPS32-O32-NEXT: fill.h $w0, $1
+; MIPS32-O32-NEXT: fexupr.w $w0, $w0
+; MIPS32-O32-NEXT: copy_s.w $1, $w0[0]
+; MIPS32-O32-NEXT: lw $25, %call16(fmaxf)($gp)
+; MIPS32-O32-NEXT: jalr $25
+; MIPS32-O32-NEXT: mtc1 $1, $f12
+; MIPS32-O32-NEXT: mfc1 $1, $f0
+; MIPS32-O32-NEXT: fill.w $w0, $1
+; MIPS32-O32-NEXT: fexdo.h $w0, $w0, $w0
+; MIPS32-O32-NEXT: copy_u.h $1, $w0[0]
+; MIPS32-O32-NEXT: sh $1, 0($16)
+; MIPS32-O32-NEXT: lw $16, 16($sp) # 4-byte Folded Reload
+; MIPS32-O32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
+; MIPS32-O32-NEXT: jr $ra
+; MIPS32-O32-NEXT: addiu $sp, $sp, 24
;
-; MIPS64-N32-LABEL: fmaxnum:
-; MIPS64-N32: # %bb.0: # %entry
-; MIPS64-N32-NEXT: addiu $sp, $sp, -32
-; MIPS64-N32-NEXT: .cfi_def_cfa_offset 32
-; MIPS64-N32-NEXT: sd $ra, 24($sp) # 8-byte Folded Spill
-; MIPS64-N32-NEXT: sd $gp, 16($sp) # 8-byte Folded Spill
-; MIPS64-N32-NEXT: sd $16, 8($sp) # 8-byte Folded Spill
-; MIPS64-N32-NEXT: .cfi_offset 31, -8
-; MIPS64-N32-NEXT: .cfi_offset 28, -16
-; MIPS64-N32-NEXT: .cfi_offset 16, -24
-; MIPS64-N32-NEXT: lui $1, %hi(%neg(%gp_rel(fmaxnum)))
-; MIPS64-N32-NEXT: addu $1, $1, $25
-; MIPS64-N32-NEXT: addiu $gp, $1, %lo(%neg(%gp_rel(fmaxnum)))
-; MIPS64-N32-NEXT: mov.s $f13, $f12
-; MIPS64-N32-NEXT: lw $16, %got_disp(g)($gp)
-; MIPS64-N32-NEXT: lh $1, 0($16)
-; MIPS64-N32-NEXT: fill.h $w0, $1
-; MIPS64-N32-NEXT: fexupr.w $w0, $w0
-; MIPS64-N32-NEXT: copy_s.w $1, $w0[0]
-; MIPS64-N32-NEXT: lw $25, %call16(fmaxf)($gp)
-; MIPS64-N32-NEXT: jalr $25
-; MIPS64-N32-NEXT: mtc1 $1, $f12
-; MIPS64-N32-NEXT: mfc1 $1, $f0
-; MIPS64-N32-NEXT: fill.w $w0, $1
-; MIPS64-N32-NEXT: fexdo.h $w0, $w0, $w0
-; MIPS64-N32-NEXT: copy_u.h $1, $w0[0]
-; MIPS64-N32-NEXT: sh $1, 0($16)
-; MIPS64-N32-NEXT: ld $16, 8($sp) # 8-byte Folded Reload
-; MIPS64-N32-NEXT: ld $gp, 16($sp) # 8-byte Folded Reload
-; MIPS64-N32-NEXT: ld $ra, 24($sp) # 8-byte Folded Reload
-; MIPS64-N32-NEXT: jr $ra
-; MIPS64-N32-NEXT: addiu $sp, $sp, 32
+; MIPS64R5-N32-LABEL: fmaxnum:
+; MIPS64R5-N32: # %bb.0: # %entry
+; MIPS64R5-N32-NEXT: addiu $sp, $sp, -32
+; MIPS64R5-N32-NEXT: .cfi_def_cfa_offset 32
+; MIPS64R5-N32-NEXT: sd $ra, 24($sp) # 8-byte Folded Spill
+; MIPS64R5-N32-NEXT: sd $gp, 16($sp) # 8-byte Folded Spill
+; MIPS64R5-N32-NEXT: sd $16, 8($sp) # 8-byte Folded Spill
+; MIPS64R5-N32-NEXT: .cfi_offset 31, -8
+; MIPS64R5-N32-NEXT: .cfi_offset 28, -16
+; MIPS64R5-N32-NEXT: .cfi_offset 16, -24
+; MIPS64R5-N32-NEXT: lui $1, %hi(%neg(%gp_rel(fmaxnum)))
+; MIPS64R5-N32-NEXT: addu $1, $1, $25
+; MIPS64R5-N32-NEXT: addiu $gp, $1, %lo(%neg(%gp_rel(fmaxnum)))
+; MIPS64R5-N32-NEXT: mov.s $f13, $f12
+; MIPS64R5-N32-NEXT: lw $16, %got_disp(g)($gp)
+; MIPS64R5-N32-NEXT: lh $1, 0($16)
+; MIPS64R5-N32-NEXT: fill.h $w0, $1
+; MIPS64R5-N32-NEXT: fexupr.w $w0, $w0
+; MIPS64R5-N32-NEXT: copy_s.w $1, $w0[0]
+; MIPS64R5-N32-NEXT: lw $25, %call16(fmaxf)($gp)
+; MIPS64R5-N32-NEXT: jalr $25
+; MIPS64R5-N32-NEXT: mtc1 $1, $f12
+; MIPS64R5-N32-NEXT: mfc1 $1, $f0
+; MIPS64R5-N32-NEXT: fill.w $w0, $1
+; MIPS64R5-N32-NEXT: fexdo.h $w0, $w0, $w0
+; MIPS64R5-N32-NEXT: copy_u.h $1, $w0[0]
+; MIPS64R5-N32-NEXT: sh $1, 0($16)
+; MIPS64R5-N32-NEXT: ld $16, 8($sp) # 8-byte Folded Reload
+; MIPS64R5-N32-NEXT: ld $gp, 16($sp) # 8-byte Folded Reload
+; MIPS64R5-N32-NEXT: ld $ra, 24($sp) # 8-byte Folded Reload
+; MIPS64R5-N32-NEXT: jr $ra
+; MIPS64R5-N32-NEXT: addiu $sp, $sp, 32
;
-; MIPS64-N64-LABEL: fmaxnum:
-; MIPS64-N64: # %bb.0: # %entry
-; MIPS64-N64-NEXT: daddiu $sp, $sp, -32
-; MIPS64-N64-NEXT: .cfi_def_cfa_offset 32
-; MIPS64-N64-NEXT: sd $ra, 24($sp) # 8-byte Folded Spill
-; MIPS64-N64-NEXT: sd $gp, 16($sp) # 8-byte Folded Spill
-; MIPS64-N64-NEXT: sd $16, 8($sp) # 8-byte Folded Spill
-; MIPS64-N64-NEXT: .cfi_offset 31, -8
-; MIPS64-N64-NEXT: .cfi_offset 28, -16
-; MIPS64-N64-NEXT: .cfi_offset 16, -24
-; MIPS64-N64-NEXT: lui $1, %hi(%neg(%gp_rel(fmaxnum)))
-; MIPS64-N64-NEXT: daddu $1, $1, $25
-; MIPS64-N64-NEXT: daddiu $gp, $1, %lo(%neg(%gp_rel(fmaxnum)))
-; MIPS64-N64-NEXT: mov.s $f13, $f12
-; MIPS64-N64-NEXT: ld $16, %got_disp(g)($gp)
-; MIPS64-N64-NEXT: lh $1, 0($16)
-; MIPS64-N64-NEXT: fill.h $w0, $1
-; MIPS64-N64-NEXT: fexupr.w $w0, $w0
-; MIPS64-N64-NEXT: copy_s.w $1, $w0[0]
-; MIPS64-N64-NEXT: ld $25, %call16(fmaxf)($gp)
-; MIPS64-N64-NEXT: jalr $25
-; MIPS64-N64-NEXT: mtc1 $1, $f12
-; MIPS64-N64-NEXT: mfc1 $1, $f0
-; MIPS64-N64-NEXT: fill.w $w0, $1
-; MIPS64-N64-NEXT: fexdo.h $w0, $w0, $w0
-; MIPS64-N64-NEXT: copy_u.h $1, $w0[0]
-; MIPS64-N64-NEXT: sh $1, 0($16)
-; MIPS64-N64-NEXT: ld $16, 8($sp) # 8-byte Folded Reload
-; MIPS64-N64-NEXT: ld $gp, 16($sp) # 8-byte Folded Reload
-; MIPS64-N64-NEXT: ld $ra, 24($sp) # 8-byte Folded Reload
-; MIPS64-N64-NEXT: jr $ra
-; MIPS64-N64-NEXT: daddiu $sp, $sp, 32
+; MIPS64R5-N64-LABEL: fmaxnum:
+; MIPS64R5-N64: # %bb.0: # %entry
+; MIPS64R5-N64-NEXT: daddiu $sp, $sp, -32
+; MIPS64R5-N64-NEXT: .cfi_def_cfa_offset 32
+; MIPS64R5-N64-NEXT: sd $ra, 24($sp) # 8-byte Folded Spill
+; MIPS64R5-N64-NEXT: sd $gp, 16($sp) # 8-byte Folded Spill
+; MIPS64R5-N64-NEXT: sd $16, 8($sp) # 8-byte Folded Spill
+; MIPS64R5-N64-NEXT: .cfi_offset 31, -8
+; MIPS64R5-N64-NEXT: .cfi_offset 28, -16
+; MIPS64R5-N64-NEXT: .cfi_offset 16, -24
+; MIPS64R5-N64-NEXT: lui $1, %hi(%neg(%gp_rel(fmaxnum)))
+; MIPS64R5-N64-NEXT: daddu $1, $1, $25
+; MIPS64R5-N64-NEXT: daddiu $gp, $1, %lo(%neg(%gp_rel(fmaxnum)))
+; MIPS64R5-N64-NEXT: mov.s $f13, $f12
+; MIPS64R5-N64-NEXT: ld $16, %got_disp(g)($gp)
+; MIPS64R5-N64-NEXT: lh $1, 0($16)
+; MIPS64R5-N64-NEXT: fill.h $w0, $1
+; MIPS64R5-N64-NEXT: fexupr.w $w0, $w0
+; MIPS64R5-N64-NEXT: copy_s.w $1, $w0[0]
+; MIPS64R5-N64-NEXT: ld $25, %call16(fmaxf)($gp)
+; MIPS64R5-N64-NEXT: jalr $25
+; MIPS64R5-N64-NEXT: mtc1 $1, $f12
+; MIPS64R5-N64-NEXT: mfc1 $1, $f0
+; MIPS64R5-N64-NEXT: fill.w $w0, $1
+; MIPS64R5-N64-NEXT: fexdo.h $w0, $w0, $w0
+; MIPS64R5-N64-NEXT: copy_u.h $1, $w0[0]
+; MIPS64R5-N64-NEXT: sh $1, 0($16)
+; MIPS64R5-N64-NEXT: ld $16, 8($sp) # 8-byte Folded Reload
+; MIPS64R5-N64-NEXT: ld $gp, 16($sp) # 8-byte Folded Reload
+; MIPS64R5-N64-NEXT: ld $ra, 24($sp) # 8-byte Folded Reload
+; MIPS64R5-N64-NEXT: jr $ra
+; MIPS64R5-N64-NEXT: daddiu $sp, $sp, 32
+;
+; MIPSR6-O32-LABEL: fmaxnum:
+; MIPSR6-O32: # %bb.0:
+; MIPSR6-O32-NEXT: lui $2, %hi(_gp_disp)
+; MIPSR6-O32-NEXT: addiu $2, $2, %lo(_gp_disp)
+; MIPSR6-O32-NEXT: addu $1, $2, $25
+; MIPSR6-O32-NEXT: lw $1, %got(g)($1)
+; MIPSR6-O32-NEXT: lh $2, 0($1)
+; MIPSR6-O32-NEXT: fill.h $w0, $2
+; MIPSR6-O32-NEXT: fexupr.w $w0, $w0
+; MIPSR6-O32-NEXT: copy_s.w $2, $w0[0]
+; MIPSR6-O32-NEXT: mtc1 $2, $f0
+; MIPSR6-O32-NEXT: max.s $f0, $f0, $f12
+; MIPSR6-O32-NEXT: mfc1 $2, $f0
+; MIPSR6-O32-NEXT: fill.w $w0, $2
+; MIPSR6-O32-NEXT: fexdo.h $w0, $w0, $w0
+; MIPSR6-O32-NEXT: copy_u.h $2, $w0[0]
+; MIPSR6-O32-NEXT: jr $ra
+; MIPSR6-O32-NEXT: sh $2, 0($1)
+;
+; MIPSR6-N32-LABEL: fmaxnum:
+; MIPSR6-N32: # %bb.0:
+; MIPSR6-N32-NEXT: lui $1, %hi(%neg(%gp_rel(fmaxnum)))
+; MIPSR6-N32-NEXT: addu $1, $1, $25
+; MIPSR6-N32-NEXT: addiu $1, $1, %lo(%neg(%gp_rel(fmaxnum)))
+; MIPSR6-N32-NEXT: lw $1, %got_disp(g)($1)
+; MIPSR6-N32-NEXT: lh $2, 0($1)
+; MIPSR6-N32-NEXT: fill.h $w0, $2
+; MIPSR6-N32-NEXT: fexupr.w $w0, $w0
+; MIPSR6-N32-NEXT: copy_s.w $2, $w0[0]
+; MIPSR6-N32-NEXT: mtc1 $2, $f0
+; MIPSR6-N32-NEXT: max.s $f0, $f0, $f12
+; MIPSR6-N32-NEXT: mfc1 $2, $f0
+; MIPSR6-N32-NEXT: fill.w $w0, $2
+; MIPSR6-N32-NEXT: fexdo.h $w0, $w0, $w0
+; MIPSR6-N32-NEXT: copy_u.h $2, $w0[0]
+; MIPSR6-N32-NEXT: jr $ra
+; MIPSR6-N32-NEXT: sh $2, 0($1)
+;
+; MIPSR6-N64-LABEL: fmaxnum:
+; MIPSR6-N64: # %bb.0:
+; MIPSR6-N64-NEXT: lui $1, %hi(%neg(%gp_rel(fmaxnum)))
+; MIPSR6-N64-NEXT: daddu $1, $1, $25
+; MIPSR6-N64-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(fmaxnum)))
+; MIPSR6-N64-NEXT: ld $1, %got_disp(g)($1)
+; MIPSR6-N64-NEXT: lh $2, 0($1)
+; MIPSR6-N64-NEXT: fill.h $w0, $2
+; MIPSR6-N64-NEXT: fexupr.w $w0, $w0
+; MIPSR6-N64-NEXT: copy_s.w $2, $w0[0]
+; MIPSR6-N64-NEXT: mtc1 $2, $f0
+; MIPSR6-N64-NEXT: max.s $f0, $f0, $f12
+; MIPSR6-N64-NEXT: mfc1 $2, $f0
+; MIPSR6-N64-NEXT: fill.w $w0, $2
+; MIPSR6-N64-NEXT: fexdo.h $w0, $w0, $w0
+; MIPSR6-N64-NEXT: copy_u.h $2, $w0[0]
+; MIPSR6-N64-NEXT: jr $ra
+; MIPSR6-N64-NEXT: sh $2, 0($1)
entry:
%0 = load i16, ptr @g, align 2
%1 = call float @llvm.convert.from.fp16.f32(i16 %0)
diff --git a/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt b/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt
index 1a73178a1f6a7e..d6f10e96d4769f 100644
--- a/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt
@@ -116,14 +116,14 @@
0x10 0x08 0x02 0x46 # CHECK: sel.s $f0, $f1, $f2
0x35 0x10 0x64 0x00 # CHECK: seleqz $2, $3, $4
0x37 0x10 0x64 0x00 # CHECK: selnez $2, $3, $4
-0x1d 0x10 0x04 0x46 # CHECK: max.s $f0, $f2, $f4
-0x1d 0x10 0x24 0x46 # CHECK: max.d $f0, $f2, $f4
0x1c 0x10 0x04 0x46 # CHECK: min.s $f0, $f2, $f4
0x1c 0x10 0x24 0x46 # CHECK: min.d $f0, $f2, $f4
+0x1d 0x10 0x04 0x46 # CHECK: mina.s $f0, $f2, $f4
+0x1d 0x10 0x24 0x46 # CHECK: mina.d $f0, $f2, $f4
+0x1e 0x10 0x04 0x46 # CHECK: max.s $f0, $f2, $f4
+0x1e 0x10 0x24 0x46 # CHECK: max.d $f0, $f2, $f4
0x1f 0x10 0x04 0x46 # CHECK: maxa.s $f0, $f2, $f4
0x1f 0x10 0x24 0x46 # CHECK: maxa.d $f0, $f2, $f4
-0x1e 0x10 0x04 0x46 # CHECK: mina.s $f0, $f2, $f4
-0x1e 0x10 0x24 0x46 # CHECK: mina.d $f0, $f2, $f4
0x04 0x00 0x42 0x34 # CHECK: ori $2, $2, 4
0x14 0x10 0x04 0x46 # CHECK: seleqz.s $f0, $f2, $f4
0x14 0x10 0x24 0x46 # CHECK: seleqz.d $f0, $f2, $f4
diff --git a/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt b/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
index 53ea0258e1c4bc..e1ba009f3c4c8c 100644
--- a/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
@@ -92,8 +92,8 @@
0x46 0x04 0x10 0x14 # CHECK: seleqz.s $f0, $f2, $f4
0x46 0x04 0x10 0x17 # CHECK: selnez.s $f0, $f2, $f4
0x46 0x04 0x10 0x1c # CHECK: min.s $f0, $f2, $f4
-0x46 0x04 0x10 0x1d # CHECK: max.s $f0, $f2, $f4
-0x46 0x04 0x10 0x1e # CHECK: mina.s $f0, $f2, $f4
+0x46 0x04 0x10 0x1d # CHECK: mina.s $f0, $f2, $f4
+0x46 0x04 0x10 0x1e # CHECK: max.s $f0, $f2, $f4
0x46 0x04 0x10 0x1f # CHECK: maxa.s $f0, $f2, $f4
0x46 0x04 0x18 0x98 # CHECK: maddf.s $f2, $f3, $f4
0x46 0x04 0x18 0x99 # CHECK: msubf.s $f2, $f3, $f4
@@ -103,8 +103,8 @@
0x46 0x24 0x10 0x14 # CHECK: seleqz.d $f0, $f2, $f4
0x46 0x24 0x10 0x17 # CHECK: selnez.d $f0, $f2, $f4
0x46 0x24 0x10 0x1c # CHECK: min.d $f0, $f2, $f4
-0x46 0x24 0x10 0x1d # CHECK: max.d $f0, $f2, $f4
-0x46 0x24 0x10 0x1e # CHECK: mina.d $f0, $f2, $f4
+0x46 0x24 0x10 0x1d # CHECK: mina.d $f0, $f2, $f4
+0x46 0x24 0x10 0x1e # CHECK: max.d $f0, $f2, $f4
0x46 0x24 0x10 0x1f # CHECK: maxa.d $f0, $f2, $f4
0x46 0x24 0x18 0x98 # CHECK: maddf.d $f2, $f3, $f4
0x46 0x24 0x18 0x99 # CHECK: msubf.d $f2, $f3, $f4
diff --git a/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt b/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
index 9aeea45472aebb..a7dfbd209b4e48 100644
--- a/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
@@ -140,15 +140,15 @@
0x43 0x00 0x50 0xec # CHECK: lwupc $2, 268
0x98 0x18 0x24 0x46 # CHECK: maddf.d $f2, $f3, $f4
0x98 0x18 0x04 0x46 # CHECK: maddf.s $f2, $f3, $f4
-0x1d 0x10 0x24 0x46 # CHECK: max.d $f0, $f2, $f4
-0x1d 0x10 0x04 0x46 # CHECK: max.s $f0, $f2, $f4
+0x1e 0x10 0x24 0x46 # CHECK: max.d $f0, $f2, $f4
+0x1e 0x10 0x04 0x46 # CHECK: max.s $f0, $f2, $f4
0x1f 0x10 0x24 0x46 # CHECK: maxa.d $f0, $f2, $f4
0x1f 0x10 0x04 0x46 # CHECK: maxa.s $f0, $f2, $f4
0x01 0x78 0x08 0x40 # CHECK: mfc0 $8, $15, 1
0x1c 0x10 0x24 0x46 # CHECK: min.d $f0, $f2, $f4
0x1c 0x10 0x04 0x46 # CHECK: min.s $f0, $f2, $f4
-0x1e 0x10 0x24 0x46 # CHECK: mina.d $f0, $f2, $f4
-0x1e 0x10 0x04 0x46 # CHECK: mina.s $f0, $f2, $f4
+0x1d 0x10 0x24 0x46 # CHECK: mina.d $f0, $f2, $f4
+0x1d 0x10 0x04 0x46 # CHECK: mina.s $f0, $f2, $f4
0xda 0x10 0x64 0x00 # CHECK: mod $2, $3, $4
0xdb 0x10 0x64 0x00 # CHECK: modu $2, $3, $4
0x25 0x78 0xe0 0x03 # CHECK: move $15, $ra
diff --git a/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt b/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
index 32b91c6c6842e1..0030e51d6c2387 100644
--- a/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
@@ -111,8 +111,8 @@
0x46 0x04 0x10 0x14 # CHECK: seleqz.s $f0, $f2, $f4
0x46 0x04 0x10 0x17 # CHECK: selnez.s $f0, $f2, $f4
0x46 0x04 0x10 0x1c # CHECK: min.s $f0, $f2, $f4
-0x46 0x04 0x10 0x1d # CHECK: max.s $f0, $f2, $f4
-0x46 0x04 0x10 0x1e # CHECK: mina.s $f0, $f2, $f4
+0x46 0x04 0x10 0x1d # CHECK: mina.s $f0, $f2, $f4
+0x46 0x04 0x10 0x1e # CHECK: max.s $f0, $f2, $f4
0x46 0x04 0x10 0x1f # CHECK: maxa.s $f0, $f2, $f4
0x46 0x04 0x18 0x98 # CHECK: maddf.s $f2, $f3, $f4
0x46 0x04 0x18 0x99 # CHECK: msubf.s $f2, $f3, $f4
@@ -122,8 +122,8 @@
0x46 0x24 0x10 0x14 # CHECK: seleqz.d $f0, $f2, $f4
0x46 0x24 0x10 0x17 # CHECK: selnez.d $f0, $f2, $f4
0x46 0x24 0x10 0x1c # CHECK: min.d $f0, $f2, $f4
-0x46 0x24 0x10 0x1d # CHECK: max.d $f0, $f2, $f4
-0x46 0x24 0x10 0x1e # CHECK: mina.d $f0, $f2, $f4
+0x46 0x24 0x10 0x1d # CHECK: mina.d $f0, $f2, $f4
+0x46 0x24 0x10 0x1e # CHECK: max.d $f0, $f2, $f4
0x46 0x24 0x10 0x1f # CHECK: maxa.d $f0, $f2, $f4
0x46 0x24 0x18 0x98 # CHECK: maddf.d $f2, $f3, $f4
0x46 0x24 0x18 0x99 # CHECK: msubf.d $f2, $f3, $f4
diff --git a/llvm/test/MC/Mips/mips32r6/valid.s b/llvm/test/MC/Mips/mips32r6/valid.s
index 0f098a176a67cc..0d705b6f242615 100644
--- a/llvm/test/MC/Mips/mips32r6/valid.s
+++ b/llvm/test/MC/Mips/mips32r6/valid.s
@@ -170,14 +170,14 @@ a:
sel.s $f0,$f1,$f2 # CHECK: sel.s $f0, $f1, $f2 # encoding: [0x46,0x02,0x08,0x10]
seleqz $2,$3,$4 # CHECK: seleqz $2, $3, $4 # encoding: [0x00,0x64,0x10,0x35]
selnez $2,$3,$4 # CHECK: selnez $2, $3, $4 # encoding: [0x00,0x64,0x10,0x37]
- max.s $f0, $f2, $f4 # CHECK: max.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1d]
- max.d $f0, $f2, $f4 # CHECK: max.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1d]
+ max.s $f0, $f2, $f4 # CHECK: max.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1e]
+ max.d $f0, $f2, $f4 # CHECK: max.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1e]
min.s $f0, $f2, $f4 # CHECK: min.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1c]
min.d $f0, $f2, $f4 # CHECK: min.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1c]
maxa.s $f0, $f2, $f4 # CHECK: maxa.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1f]
maxa.d $f0, $f2, $f4 # CHECK: maxa.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1f]
- mina.s $f0, $f2, $f4 # CHECK: mina.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1e]
- mina.d $f0, $f2, $f4 # CHECK: mina.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1e]
+ mina.s $f0, $f2, $f4 # CHECK: mina.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1d]
+ mina.d $f0, $f2, $f4 # CHECK: mina.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1d]
or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04]
seleqz.s $f0, $f2, $f4 # CHECK: seleqz.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x14]
seleqz.d $f0, $f2, $f4 # CHECK: seleqz.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x14]
diff --git a/llvm/test/MC/Mips/mips64r6/valid.s b/llvm/test/MC/Mips/mips64r6/valid.s
index c50bd9e31c232e..ff6e1d73fbeb48 100644
--- a/llvm/test/MC/Mips/mips64r6/valid.s
+++ b/llvm/test/MC/Mips/mips64r6/valid.s
@@ -183,14 +183,14 @@ a:
lwupc $2,268 # CHECK: lwupc $2, 268 # encoding: [0xec,0x50,0x00,0x43]
maddf.d $f2,$f3,$f4 # CHECK: maddf.d $f2, $f3, $f4 # encoding: [0x46,0x24,0x18,0x98]
maddf.s $f2,$f3,$f4 # CHECK: maddf.s $f2, $f3, $f4 # encoding: [0x46,0x04,0x18,0x98]
- max.d $f0, $f2, $f4 # CHECK: max.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1d]
- max.s $f0, $f2, $f4 # CHECK: max.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1d]
+ max.d $f0, $f2, $f4 # CHECK: max.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1e]
+ max.s $f0, $f2, $f4 # CHECK: max.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1e]
maxa.d $f0, $f2, $f4 # CHECK: maxa.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1f]
maxa.s $f0, $f2, $f4 # CHECK: maxa.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1f]
min.d $f0, $f2, $f4 # CHECK: min.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1c]
min.s $f0, $f2, $f4 # CHECK: min.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1c]
- mina.d $f0, $f2, $f4 # CHECK: mina.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1e]
- mina.s $f0, $f2, $f4 # CHECK: mina.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1e]
+ mina.d $f0, $f2, $f4 # CHECK: mina.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1d]
+ mina.s $f0, $f2, $f4 # CHECK: mina.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1d]
mfc0 $8,$15,1 # CHECK: mfc0 $8, $15, 1 # encoding: [0x40,0x08,0x78,0x01]
mod $2,$3,$4 # CHECK: mod $2, $3, $4 # encoding: [0x00,0x64,0x10,0xda]
modu $2,$3,$4 # CHECK: modu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdb]
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