[llvm] [MachineFrameInfo] Refactoring with computeMaxcallFrameSize() (NFC) (PR #78001)
Jonas Paulsson via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 18 07:35:15 PDT 2024
https://github.com/JonPsson1 updated https://github.com/llvm/llvm-project/pull/78001
>From 2fe4bc27f2377cd61b7124ebae35c2ffba9289f0 Mon Sep 17 00:00:00 2001
From: Jonas Paulsson <paulson1 at linux.ibm.com>
Date: Fri, 12 Jan 2024 15:16:45 -0600
Subject: [PATCH 1/2] IP Only do the code-duplication fix. Set AdjustsStack in
finalize isel. Add assert in PEI and fix backends/mir-tests.
---
llvm/include/llvm/CodeGen/MachineFrameInfo.h | 8 +++-
llvm/include/llvm/CodeGen/TargetInstrInfo.h | 1 +
llvm/lib/CodeGen/FinalizeISel.cpp | 9 +++++
llvm/lib/CodeGen/MachineFrameInfo.cpp | 15 +++----
llvm/lib/CodeGen/PrologEpilogInserter.cpp | 40 ++++++-------------
llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp | 5 ++-
llvm/lib/Target/X86/X86ISelLowering.cpp | 1 +
llvm/test/CodeGen/AArch64/avoid-zero-copy.mir | 2 +
...lee-save-size-after-livedebugvariables.mir | 1 +
.../AMDGPU/av_spill_cross_bb_usage.mir | 2 +
.../Hexagon/livephysregs-regmask-clobber.mir | 2 +
.../CodeGen/MIR/AMDGPU/stack-id-assert.mir | 2 +
llvm/test/CodeGen/Mips/avoid-zero-copy.mir | 2 +
.../test/CodeGen/Mips/msa/emergency-spill.mir | 2 +-
llvm/test/CodeGen/RISCV/live-sp.mir | 2 +-
.../RISCV/rvv/addi-rvv-stack-object.mir | 2 +-
.../CodeGen/RISCV/rvv/rvv-stack-align.mir | 6 +--
.../rvv/wrong-stack-offset-for-rvv-object.mir | 2 +-
.../CodeGen/RISCV/stack-inst-compress.mir | 3 ++
llvm/test/CodeGen/SystemZ/cond-move-04.mir | 1 +
llvm/test/CodeGen/SystemZ/cond-move-08.mir | 1 +
.../SystemZ/cond-move-regalloc-hints-02.mir | 1 +
.../SystemZ/cond-move-regalloc-hints.mir | 1 +
llvm/test/CodeGen/SystemZ/frame-28.mir | 2 +
.../fast-regalloc-live-out-debug-values.mir | 1 +
llvm/test/CodeGen/X86/heap-alloc-markers.mir | 1 +
llvm/test/CodeGen/X86/instr-symbols.mir | 1 +
.../CodeGen/X86/statepoint-fixup-undef.mir | 2 +-
llvm/test/CodeGen/X86/statepoint-vreg.mir | 2 +
29 files changed, 72 insertions(+), 48 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/MachineFrameInfo.h b/llvm/include/llvm/CodeGen/MachineFrameInfo.h
index 7d11d63d4066f4..0fe73fec7ee67f 100644
--- a/llvm/include/llvm/CodeGen/MachineFrameInfo.h
+++ b/llvm/include/llvm/CodeGen/MachineFrameInfo.h
@@ -638,13 +638,17 @@ class MachineFrameInfo {
bool hasTailCall() const { return HasTailCall; }
void setHasTailCall(bool V = true) { HasTailCall = V; }
- /// Computes the maximum size of a callframe and the AdjustsStack property.
+ /// Computes the maximum size of a callframe.
/// This only works for targets defining
/// TargetInstrInfo::getCallFrameSetupOpcode(), getCallFrameDestroyOpcode(),
/// and getFrameSize().
/// This is usually computed by the prologue epilogue inserter but some
/// targets may call this to compute it earlier.
- void computeMaxCallFrameSize(const MachineFunction &MF);
+ /// If FrameSDOps is passed, the frame instructions in the MF will be
+ /// inserted into it.
+ void computeMaxCallFrameSize(
+ MachineFunction &MF,
+ std::vector<MachineBasicBlock::iterator> *FrameSDOps = nullptr);
/// Return the maximum size of a call frame that must be
/// allocated for an outgoing function call. This is only available if
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index be4ee5b6f9e29a..9fd0ebe6956fbe 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -204,6 +204,7 @@ class TargetInstrInfo : public MCInstrInfo {
/// if they exist (-1 otherwise). Some targets use pseudo instructions in
/// order to abstract away the difference between operating with a frame
/// pointer and operating without, through the use of these two instructions.
+ /// A FrameSetup MI in MF implies MFI::AdjustsStack.
///
unsigned getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
unsigned getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
diff --git a/llvm/lib/CodeGen/FinalizeISel.cpp b/llvm/lib/CodeGen/FinalizeISel.cpp
index 329c9587e32122..978355f8eb1bbf 100644
--- a/llvm/lib/CodeGen/FinalizeISel.cpp
+++ b/llvm/lib/CodeGen/FinalizeISel.cpp
@@ -14,8 +14,10 @@
//
//===----------------------------------------------------------------------===//
+#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/InitializePasses.h"
@@ -45,6 +47,7 @@ INITIALIZE_PASS(FinalizeISel, DEBUG_TYPE,
bool FinalizeISel::runOnMachineFunction(MachineFunction &MF) {
bool Changed = false;
+ const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
const TargetLowering *TLI = MF.getSubtarget().getTargetLowering();
// Iterate through each instruction in the function, looking for pseudos.
@@ -54,6 +57,12 @@ bool FinalizeISel::runOnMachineFunction(MachineFunction &MF) {
MBBI != MBBE; ) {
MachineInstr &MI = *MBBI++;
+ // Set AdjustsStack to true if the instruction selector emits a stack
+ // frame setup instruction or a stack aligning inlineasm.
+ if (MI.getOpcode() == TII->getCallFrameSetupOpcode() ||
+ MI.isStackAligningInlineAsm())
+ MF.getFrameInfo().setAdjustsStack(true);
+
// If MI is a pseudo, expand it.
if (MI.usesCustomInsertionHook()) {
Changed = true;
diff --git a/llvm/lib/CodeGen/MachineFrameInfo.cpp b/llvm/lib/CodeGen/MachineFrameInfo.cpp
index 280d3a6a41edc9..853de4c88caeb7 100644
--- a/llvm/lib/CodeGen/MachineFrameInfo.cpp
+++ b/llvm/lib/CodeGen/MachineFrameInfo.cpp
@@ -184,7 +184,8 @@ uint64_t MachineFrameInfo::estimateStackSize(const MachineFunction &MF) const {
return alignTo(Offset, StackAlign);
}
-void MachineFrameInfo::computeMaxCallFrameSize(const MachineFunction &MF) {
+void MachineFrameInfo::computeMaxCallFrameSize(
+ MachineFunction &MF, std::vector<MachineBasicBlock::iterator> *FrameSDOps) {
const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
unsigned FrameSetupOpcode = TII.getCallFrameSetupOpcode();
unsigned FrameDestroyOpcode = TII.getCallFrameDestroyOpcode();
@@ -192,18 +193,14 @@ void MachineFrameInfo::computeMaxCallFrameSize(const MachineFunction &MF) {
"Can only compute MaxCallFrameSize if Setup/Destroy opcode are known");
MaxCallFrameSize = 0;
- for (const MachineBasicBlock &MBB : MF) {
- for (const MachineInstr &MI : MBB) {
+ for (MachineBasicBlock &MBB : MF) {
+ for (MachineInstr &MI : MBB) {
unsigned Opcode = MI.getOpcode();
if (Opcode == FrameSetupOpcode || Opcode == FrameDestroyOpcode) {
unsigned Size = TII.getFrameSize(MI);
MaxCallFrameSize = std::max(MaxCallFrameSize, Size);
- AdjustsStack = true;
- } else if (MI.isInlineAsm()) {
- // Some inline asm's need a stack frame, as indicated by operand 1.
- unsigned ExtraInfo = MI.getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
- if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
- AdjustsStack = true;
+ if (FrameSDOps != nullptr)
+ FrameSDOps->push_back(&MI);
}
}
}
diff --git a/llvm/lib/CodeGen/PrologEpilogInserter.cpp b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
index 8af17e63e25c75..e77d5e658962b1 100644
--- a/llvm/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
@@ -228,9 +228,8 @@ bool PEI::runOnMachineFunction(MachineFunction &MF) {
FrameIndexVirtualScavenging = TRI->requiresFrameIndexScavenging(MF);
ORE = &getAnalysis<MachineOptimizationRemarkEmitterPass>().getORE();
- // Calculate the MaxCallFrameSize and AdjustsStack variables for the
- // function's frame information. Also eliminates call frame pseudo
- // instructions.
+ // Calculate the MaxCallFrameSize value for the function's frame
+ // information. Also eliminates call frame pseudo instructions.
calculateCallFrameInfo(MF);
// Determine placement of CSR spill/restore code and prolog/epilog code:
@@ -350,17 +349,13 @@ bool PEI::runOnMachineFunction(MachineFunction &MF) {
return true;
}
-/// Calculate the MaxCallFrameSize and AdjustsStack
-/// variables for the function's frame information and eliminate call frame
-/// pseudo instructions.
+/// Calculate the MaxCallFrameSize variable for the function's frame
+/// information and eliminate call frame pseudo instructions.
void PEI::calculateCallFrameInfo(MachineFunction &MF) {
const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
MachineFrameInfo &MFI = MF.getFrameInfo();
- unsigned MaxCallFrameSize = 0;
- bool AdjustsStack = MFI.adjustsStack();
-
// Get the function call frame set-up and tear-down instruction opcode
unsigned FrameSetupOpcode = TII.getCallFrameSetupOpcode();
unsigned FrameDestroyOpcode = TII.getCallFrameDestroyOpcode();
@@ -370,26 +365,15 @@ void PEI::calculateCallFrameInfo(MachineFunction &MF) {
if (FrameSetupOpcode == ~0u && FrameDestroyOpcode == ~0u)
return;
+ // (Re-)Compute the MaxCallFrameSize.
+ uint32_t MaxCFSIn =
+ MFI.isMaxCallFrameSizeComputed() ? MFI.getMaxCallFrameSize() : UINT32_MAX;
std::vector<MachineBasicBlock::iterator> FrameSDOps;
- for (MachineBasicBlock &BB : MF)
- for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I)
- if (TII.isFrameInstr(*I)) {
- unsigned Size = TII.getFrameSize(*I);
- if (Size > MaxCallFrameSize) MaxCallFrameSize = Size;
- AdjustsStack = true;
- FrameSDOps.push_back(I);
- } else if (I->isInlineAsm()) {
- // Some inline asm's need a stack frame, as indicated by operand 1.
- unsigned ExtraInfo = I->getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
- if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
- AdjustsStack = true;
- }
-
- assert(!MFI.isMaxCallFrameSizeComputed() ||
- (MFI.getMaxCallFrameSize() >= MaxCallFrameSize &&
- !(AdjustsStack && !MFI.adjustsStack())));
- MFI.setAdjustsStack(AdjustsStack);
- MFI.setMaxCallFrameSize(MaxCallFrameSize);
+ MFI.computeMaxCallFrameSize(MF, &FrameSDOps);
+ assert(MFI.getMaxCallFrameSize() <= MaxCFSIn &&
+ "Recomputing MaxCFS gave a larger value.");
+ assert((FrameSDOps.empty() || MF.getFrameInfo().adjustsStack()) &&
+ "AdjustsStack not set in presence of a frame pseudo instruction.");
if (TFI->canSimplifyCallFramePseudos(MF)) {
// If call frames are not being included as part of the stack frame, and
diff --git a/llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp b/llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp
index 147438dfedd87d..9f680ef5046dad 100644
--- a/llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp
@@ -25,6 +25,7 @@
#include "PPCInstrInfo.h"
#include "PPCTargetMachine.h"
#include "llvm/CodeGen/LiveIntervals.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/InitializePasses.h"
@@ -159,9 +160,11 @@ namespace {
// We don't really need to save data to the stack - the clobbered
// registers are already saved when the SDNode (e.g. PPCaddiTlsgdLAddr)
// gets translated to the pseudo instruction (e.g. ADDItlsgdLADDR).
- if (NeedFence)
+ if (NeedFence) {
+ MBB.getParent()->getFrameInfo().setAdjustsStack(true);
BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKDOWN)).addImm(0)
.addImm(0);
+ }
if (IsAIX) {
if (IsTLSLDAIXMI) {
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 9b88611073f01d..8a6594230f0a2c 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -35228,6 +35228,7 @@ X86TargetLowering::EmitLoweredTLSAddr(MachineInstr &MI,
MachineFunction &MF = *BB->getParent();
// Emit CALLSEQ_START right before the instruction.
+ BB->getParent()->getFrameInfo().setAdjustsStack(true);
unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
MachineInstrBuilder CallseqStart =
BuildMI(MF, MIMD, TII.get(AdjStackDown)).addImm(0).addImm(0).addImm(0);
diff --git a/llvm/test/CodeGen/AArch64/avoid-zero-copy.mir b/llvm/test/CodeGen/AArch64/avoid-zero-copy.mir
index 859be2d3374762..b940734c6988cb 100644
--- a/llvm/test/CodeGen/AArch64/avoid-zero-copy.mir
+++ b/llvm/test/CodeGen/AArch64/avoid-zero-copy.mir
@@ -19,6 +19,8 @@
...
---
name: foo
+frameInfo:
+ adjustsStack: true
body: |
bb.0 (%ir-block.0):
; CHECK-LABEL: name: foo
diff --git a/llvm/test/CodeGen/AArch64/wrong-callee-save-size-after-livedebugvariables.mir b/llvm/test/CodeGen/AArch64/wrong-callee-save-size-after-livedebugvariables.mir
index 53a8612a7fae76..8e1142474447ed 100644
--- a/llvm/test/CodeGen/AArch64/wrong-callee-save-size-after-livedebugvariables.mir
+++ b/llvm/test/CodeGen/AArch64/wrong-callee-save-size-after-livedebugvariables.mir
@@ -64,6 +64,7 @@
name: foo
tracksRegLiveness: true
frameInfo:
+ adjustsStack: true
hasCalls: true
fixedStack: []
stack:
diff --git a/llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir b/llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir
index c1da29ecc2c2f5..3228962ed01f78 100644
--- a/llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir
+++ b/llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir
@@ -14,6 +14,8 @@
---
name: test_av_spill_cross_bb_usage
tracksRegLiveness: true
+frameInfo:
+ adjustsStack: true
stack:
- { id: 0, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4 }
machineFunctionInfo:
diff --git a/llvm/test/CodeGen/Hexagon/livephysregs-regmask-clobber.mir b/llvm/test/CodeGen/Hexagon/livephysregs-regmask-clobber.mir
index 8f1cb42b96a6fa..52213070f53567 100644
--- a/llvm/test/CodeGen/Hexagon/livephysregs-regmask-clobber.mir
+++ b/llvm/test/CodeGen/Hexagon/livephysregs-regmask-clobber.mir
@@ -17,6 +17,8 @@
name: f0
tracksRegLiveness: true
+frameInfo:
+ adjustsStack: true
stack:
- { id: 0, offset: 0, size: 128, alignment: 128 }
- { id: 1, offset: 128, size: 128, alignment: 128 }
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/stack-id-assert.mir b/llvm/test/CodeGen/MIR/AMDGPU/stack-id-assert.mir
index e40d1879399cef..9831f786b847d3 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/stack-id-assert.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/stack-id-assert.mir
@@ -29,6 +29,8 @@ liveins:
- { reg: '$vgpr0', virtual-reg: '' }
- { reg: '$vgpr1', virtual-reg: '' }
- { reg: '$vgpr2', virtual-reg: '' }
+frameInfo:
+ adjustsStack: true
stack:
- { id: 0, name: '', type: spill-slot, offset: 0, size: 8, alignment: 4,
stack-id: sgpr-spill, callee-saved-register: '', callee-saved-restored: true,
diff --git a/llvm/test/CodeGen/Mips/avoid-zero-copy.mir b/llvm/test/CodeGen/Mips/avoid-zero-copy.mir
index 5c7cffd109ea62..e3990bdf9bc3fb 100644
--- a/llvm/test/CodeGen/Mips/avoid-zero-copy.mir
+++ b/llvm/test/CodeGen/Mips/avoid-zero-copy.mir
@@ -19,6 +19,8 @@
...
---
name: a
+frameInfo:
+ adjustsStack: true
body: |
bb.0 (%ir-block.0):
liveins: $a0_64, $t9_64, $ra_64, $fp_64, $gp_64
diff --git a/llvm/test/CodeGen/Mips/msa/emergency-spill.mir b/llvm/test/CodeGen/Mips/msa/emergency-spill.mir
index e1c7b2158d6174..20894645286618 100644
--- a/llvm/test/CodeGen/Mips/msa/emergency-spill.mir
+++ b/llvm/test/CodeGen/Mips/msa/emergency-spill.mir
@@ -90,7 +90,7 @@ frameInfo:
stackSize: 0
offsetAdjustment: 0
maxAlignment: 16
- adjustsStack: false
+ adjustsStack: true
hasCalls: true
stackProtector: ''
maxCallFrameSize: 4294967295
diff --git a/llvm/test/CodeGen/RISCV/live-sp.mir b/llvm/test/CodeGen/RISCV/live-sp.mir
index 8dd307f521f5bd..fa6297a3913a9b 100644
--- a/llvm/test/CodeGen/RISCV/live-sp.mir
+++ b/llvm/test/CodeGen/RISCV/live-sp.mir
@@ -44,7 +44,7 @@ frameInfo:
stackSize: 0
offsetAdjustment: 0
maxAlignment: 4
- adjustsStack: false
+ adjustsStack: true
hasCalls: true
stackProtector: ''
maxCallFrameSize: 4294967295
diff --git a/llvm/test/CodeGen/RISCV/rvv/addi-rvv-stack-object.mir b/llvm/test/CodeGen/RISCV/rvv/addi-rvv-stack-object.mir
index 52557288210394..080a89e41f0d54 100644
--- a/llvm/test/CodeGen/RISCV/rvv/addi-rvv-stack-object.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/addi-rvv-stack-object.mir
@@ -22,7 +22,7 @@ frameInfo:
stackSize: 0
offsetAdjustment: 0
maxAlignment: 16
- adjustsStack: false
+ adjustsStack: true
hasCalls: true
stackProtector: ''
functionContext: ''
diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir b/llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir
index 6ea6fb183a7fdf..749bd4c13879b6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir
@@ -159,7 +159,7 @@ frameInfo:
stackSize: 0
offsetAdjustment: 0
maxAlignment: 8
- adjustsStack: false
+ adjustsStack: true
hasCalls: true
stackProtector: ''
maxCallFrameSize: 4294967295
@@ -204,7 +204,7 @@ frameInfo:
stackSize: 0
offsetAdjustment: 0
maxAlignment: 16
- adjustsStack: false
+ adjustsStack: true
hasCalls: true
stackProtector: ''
maxCallFrameSize: 4294967295
@@ -249,7 +249,7 @@ frameInfo:
stackSize: 0
offsetAdjustment: 0
maxAlignment: 32
- adjustsStack: false
+ adjustsStack: true
hasCalls: true
stackProtector: ''
maxCallFrameSize: 4294967295
diff --git a/llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir b/llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir
index 06ed46f291a832..8248c26636793e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir
@@ -83,7 +83,7 @@ frameInfo:
stackSize: 0
offsetAdjustment: 0
maxAlignment: 8
- adjustsStack: false
+ adjustsStack: true
hasCalls: true
stackProtector: ''
maxCallFrameSize: 4294967295
diff --git a/llvm/test/CodeGen/RISCV/stack-inst-compress.mir b/llvm/test/CodeGen/RISCV/stack-inst-compress.mir
index 6721ff11d99b7b..5cc4615bb64a13 100644
--- a/llvm/test/CodeGen/RISCV/stack-inst-compress.mir
+++ b/llvm/test/CodeGen/RISCV/stack-inst-compress.mir
@@ -32,6 +32,7 @@ alignment: 2
tracksRegLiveness: true
frameInfo:
maxAlignment: 4
+ adjustsStack: true
hasCalls: true
localFrameSize: 2048
stack:
@@ -117,6 +118,7 @@ alignment: 2
tracksRegLiveness: true
frameInfo:
maxAlignment: 4
+ adjustsStack: true
hasCalls: true
localFrameSize: 4096
stack:
@@ -210,6 +212,7 @@ alignment: 2
tracksRegLiveness: true
frameInfo:
maxAlignment: 4
+ adjustsStack: true
hasCalls: true
localFrameSize: 8192
stack:
diff --git a/llvm/test/CodeGen/SystemZ/cond-move-04.mir b/llvm/test/CodeGen/SystemZ/cond-move-04.mir
index 97aa00f582921d..23fd2739698a40 100644
--- a/llvm/test/CodeGen/SystemZ/cond-move-04.mir
+++ b/llvm/test/CodeGen/SystemZ/cond-move-04.mir
@@ -53,6 +53,7 @@ registers:
- { id: 10, class: gr64bit }
- { id: 11, class: gr32bit }
frameInfo:
+ adjustsStack: true
hasCalls: true
body: |
bb.0 (%ir-block.1):
diff --git a/llvm/test/CodeGen/SystemZ/cond-move-08.mir b/llvm/test/CodeGen/SystemZ/cond-move-08.mir
index 93aa5626b8e894..64c6d069799282 100644
--- a/llvm/test/CodeGen/SystemZ/cond-move-08.mir
+++ b/llvm/test/CodeGen/SystemZ/cond-move-08.mir
@@ -116,6 +116,7 @@ registers:
- { id: 27, class: grx32bit }
- { id: 28, class: addr64bit }
frameInfo:
+ adjustsStack: true
hasCalls: true
body: |
bb.0.bb5:
diff --git a/llvm/test/CodeGen/SystemZ/cond-move-regalloc-hints-02.mir b/llvm/test/CodeGen/SystemZ/cond-move-regalloc-hints-02.mir
index 37e29800fb1d62..2701a1dc034a22 100644
--- a/llvm/test/CodeGen/SystemZ/cond-move-regalloc-hints-02.mir
+++ b/llvm/test/CodeGen/SystemZ/cond-move-regalloc-hints-02.mir
@@ -30,6 +30,7 @@ registers:
- { id: 11, class: gr32bit }
frameInfo:
maxAlignment: 1
+ adjustsStack: true
hasCalls: true
machineFunctionInfo: {}
body: |
diff --git a/llvm/test/CodeGen/SystemZ/cond-move-regalloc-hints.mir b/llvm/test/CodeGen/SystemZ/cond-move-regalloc-hints.mir
index e7e1eaf8f8fdcd..c98ffda8372721 100644
--- a/llvm/test/CodeGen/SystemZ/cond-move-regalloc-hints.mir
+++ b/llvm/test/CodeGen/SystemZ/cond-move-regalloc-hints.mir
@@ -192,6 +192,7 @@ liveins:
- { reg: '$r2d', virtual-reg: '%31' }
- { reg: '$r3d', virtual-reg: '%32' }
frameInfo:
+ adjustsStack: true
hasCalls: true
body: |
bb.0.bb:
diff --git a/llvm/test/CodeGen/SystemZ/frame-28.mir b/llvm/test/CodeGen/SystemZ/frame-28.mir
index dd5933a9c7b4b4..13337dba6ec53f 100644
--- a/llvm/test/CodeGen/SystemZ/frame-28.mir
+++ b/llvm/test/CodeGen/SystemZ/frame-28.mir
@@ -162,6 +162,8 @@ body: |
---
name: fun4
tracksRegLiveness: true
+frameInfo:
+ adjustsStack: true
stack:
- { id: 0, size: 5000 }
- { id: 1, size: 2500 }
diff --git a/llvm/test/CodeGen/X86/fast-regalloc-live-out-debug-values.mir b/llvm/test/CodeGen/X86/fast-regalloc-live-out-debug-values.mir
index 56cbe3f7b56388..37a90a2f16d671 100644
--- a/llvm/test/CodeGen/X86/fast-regalloc-live-out-debug-values.mir
+++ b/llvm/test/CodeGen/X86/fast-regalloc-live-out-debug-values.mir
@@ -119,6 +119,7 @@
name: foo
tracksRegLiveness: true
frameInfo:
+ adjustsStack: true
hasCalls: true
stack:
- { id: 0, name: a.addr, size: 4, alignment: 4, debug-info-variable: '!11',
diff --git a/llvm/test/CodeGen/X86/heap-alloc-markers.mir b/llvm/test/CodeGen/X86/heap-alloc-markers.mir
index 0bf83657cb06c0..6e0dc50bac0e19 100644
--- a/llvm/test/CodeGen/X86/heap-alloc-markers.mir
+++ b/llvm/test/CodeGen/X86/heap-alloc-markers.mir
@@ -34,6 +34,7 @@ name: test
# CHECK-LABEL: {{^}}test:
tracksRegLiveness: true
frameInfo:
+ adjustsStack: true
hasCalls: true
body: |
bb.0.entry:
diff --git a/llvm/test/CodeGen/X86/instr-symbols.mir b/llvm/test/CodeGen/X86/instr-symbols.mir
index a900288d70869a..7af6ca81810123 100644
--- a/llvm/test/CodeGen/X86/instr-symbols.mir
+++ b/llvm/test/CodeGen/X86/instr-symbols.mir
@@ -23,6 +23,7 @@ name: test
# CHECK-LABEL: {{^}}test:
tracksRegLiveness: true
frameInfo:
+ adjustsStack: true
hasCalls: true
body: |
bb.0.entry:
diff --git a/llvm/test/CodeGen/X86/statepoint-fixup-undef.mir b/llvm/test/CodeGen/X86/statepoint-fixup-undef.mir
index 30a68e6c2efd2a..4a18351bde493d 100644
--- a/llvm/test/CodeGen/X86/statepoint-fixup-undef.mir
+++ b/llvm/test/CodeGen/X86/statepoint-fixup-undef.mir
@@ -61,7 +61,7 @@ frameInfo:
stackSize: 0
offsetAdjustment: 0
maxAlignment: 8
- adjustsStack: false
+ adjustsStack: true
hasCalls: true
stackProtector: ''
maxCallFrameSize: 4294967295
diff --git a/llvm/test/CodeGen/X86/statepoint-vreg.mir b/llvm/test/CodeGen/X86/statepoint-vreg.mir
index bfeadfc93da8f6..a0c596f249931c 100644
--- a/llvm/test/CodeGen/X86/statepoint-vreg.mir
+++ b/llvm/test/CodeGen/X86/statepoint-vreg.mir
@@ -134,6 +134,8 @@ registers:
liveins:
- { reg: '$rdi', virtual-reg: '%0' }
- { reg: '$rsi', virtual-reg: '%1' }
+frameInfo:
+ adjustsStack: true
fixedStack: []
stack: []
callSites: []
>From 1b1e379ef3b279b20ca97f320487ed2375a69eae Mon Sep 17 00:00:00 2001
From: Jonas Paulsson <paulson1 at linux.ibm.com>
Date: Mon, 18 Mar 2024 10:13:30 -0400
Subject: [PATCH 2/2] More tests updated
---
llvm/test/CodeGen/AArch64/stack-probing-no-scratch-reg.mir | 1 +
llvm/test/CodeGen/AArch64/stack-probing-shrink-wrap.mir | 1 +
llvm/test/DebugInfo/MIR/X86/debug-loc-0.mir | 2 +-
llvm/test/DebugInfo/MIR/X86/prolog-epilog-indirection.mir | 1 +
llvm/test/DebugInfo/X86/live-debug-vars-dse.mir | 2 +-
llvm/test/DebugInfo/X86/prolog-params.mir | 2 ++
6 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/stack-probing-no-scratch-reg.mir b/llvm/test/CodeGen/AArch64/stack-probing-no-scratch-reg.mir
index f2d79bd7206908..a9c9b5ff60e451 100644
--- a/llvm/test/CodeGen/AArch64/stack-probing-no-scratch-reg.mir
+++ b/llvm/test/CodeGen/AArch64/stack-probing-no-scratch-reg.mir
@@ -29,6 +29,7 @@ tracksRegLiveness: true
liveins:
- { reg: '$w0', virtual-reg: '' }
frameInfo:
+ adjustsStack: true
localFrameSize: 150000
stack:
- { id: 0, name: a, type: default, offset: 0, size: 150000, alignment: 8,
diff --git a/llvm/test/CodeGen/AArch64/stack-probing-shrink-wrap.mir b/llvm/test/CodeGen/AArch64/stack-probing-shrink-wrap.mir
index 83aa90d389a4a2..985ec352139708 100644
--- a/llvm/test/CodeGen/AArch64/stack-probing-shrink-wrap.mir
+++ b/llvm/test/CodeGen/AArch64/stack-probing-shrink-wrap.mir
@@ -31,6 +31,7 @@ tracksRegLiveness: true
liveins:
- { reg: '$w0', virtual-reg: '' }
frameInfo:
+ adjustsStack: true
localFrameSize: 150000
stack:
- { id: 0, name: a, type: default, offset: 0, size: 150000, alignment: 8,
diff --git a/llvm/test/DebugInfo/MIR/X86/debug-loc-0.mir b/llvm/test/DebugInfo/MIR/X86/debug-loc-0.mir
index 56a4d835aaa597..0b007456be1e6f 100644
--- a/llvm/test/DebugInfo/MIR/X86/debug-loc-0.mir
+++ b/llvm/test/DebugInfo/MIR/X86/debug-loc-0.mir
@@ -75,7 +75,7 @@ frameInfo:
stackSize: 0
offsetAdjustment: 0
maxAlignment: 8
- adjustsStack: false
+ adjustsStack: true
hasCalls: true
stackProtector: ''
maxCallFrameSize: 4294967295
diff --git a/llvm/test/DebugInfo/MIR/X86/prolog-epilog-indirection.mir b/llvm/test/DebugInfo/MIR/X86/prolog-epilog-indirection.mir
index 6941467fe0e4a3..4df967ce034939 100644
--- a/llvm/test/DebugInfo/MIR/X86/prolog-epilog-indirection.mir
+++ b/llvm/test/DebugInfo/MIR/X86/prolog-epilog-indirection.mir
@@ -104,6 +104,7 @@ alignment: 16
tracksRegLiveness: true
frameInfo:
maxAlignment: 4
+ adjustsStack: true
hasCalls: true
stack:
- { id: 0, name: l_1081, type: default, offset: 0, size: 4, alignment: 4,
diff --git a/llvm/test/DebugInfo/X86/live-debug-vars-dse.mir b/llvm/test/DebugInfo/X86/live-debug-vars-dse.mir
index 9443ed5e332c13..908889063584c2 100644
--- a/llvm/test/DebugInfo/X86/live-debug-vars-dse.mir
+++ b/llvm/test/DebugInfo/X86/live-debug-vars-dse.mir
@@ -107,7 +107,7 @@ frameInfo:
stackSize: 0
offsetAdjustment: 0
maxAlignment: 8
- adjustsStack: false
+ adjustsStack: true
hasCalls: true
stackProtector: ''
maxCallFrameSize: 4294967295
diff --git a/llvm/test/DebugInfo/X86/prolog-params.mir b/llvm/test/DebugInfo/X86/prolog-params.mir
index af21bc85ccd746..6629dca810f954 100644
--- a/llvm/test/DebugInfo/X86/prolog-params.mir
+++ b/llvm/test/DebugInfo/X86/prolog-params.mir
@@ -98,6 +98,8 @@ fixedStack:
isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true }
- { id: 2, type: default, offset: 0, size: 4, alignment: 16, stack-id: default,
isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true }
+frameInfo:
+ adjustsStack: true
stack:
- { id: 0, name: arr, type: default, offset: 0, size: 8, alignment: 4,
stack-id: default, callee-saved-register: '', callee-saved-restored: true }
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