[llvm] 057e725 - [Sparc] Use generated MatchRegisterName (NFCI) (#82165)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 1 18:17:45 PST 2024
Author: Sergei Barannikov
Date: 2024-03-02T05:17:41+03:00
New Revision: 057e7252608e680348484c7942ac0d78bd174ec1
URL: https://github.com/llvm/llvm-project/commit/057e7252608e680348484c7942ac0d78bd174ec1
DIFF: https://github.com/llvm/llvm-project/commit/057e7252608e680348484c7942ac0d78bd174ec1.diff
LOG: [Sparc] Use generated MatchRegisterName (NFCI) (#82165)
Added:
Modified:
llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
llvm/lib/Target/Sparc/Sparc.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
index 7a956636831df7..be4ec1e9dce2a6 100644
--- a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
+++ b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
@@ -57,6 +57,7 @@ class SparcOperand;
class SparcAsmParser : public MCTargetAsmParser {
MCAsmParser &Parser;
+ const MCRegisterInfo &MRI;
enum class TailRelocKind { Load_GOT, Add_TLS, Load_TLS, Call_TLS };
@@ -109,8 +110,7 @@ class SparcAsmParser : public MCTargetAsmParser {
const MCExpr *subExpr);
// returns true if Tok is matched to a register and returns register in RegNo.
- bool matchRegisterName(const AsmToken &Tok, MCRegister &RegNo,
- unsigned &RegKind);
+ MCRegister matchRegisterName(const AsmToken &Tok, unsigned &RegKind);
bool matchSparcAsmModifiers(const MCExpr *&EVal, SMLoc &EndLoc);
@@ -128,9 +128,9 @@ class SparcAsmParser : public MCTargetAsmParser {
public:
SparcAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
- const MCInstrInfo &MII,
- const MCTargetOptions &Options)
- : MCTargetAsmParser(Options, sti, MII), Parser(parser) {
+ const MCInstrInfo &MII, const MCTargetOptions &Options)
+ : MCTargetAsmParser(Options, sti, MII), Parser(parser),
+ MRI(*Parser.getContext().getRegisterInfo()) {
Parser.addAliasForDirective(".half", ".2byte");
Parser.addAliasForDirective(".uahalf", ".2byte");
Parser.addAliasForDirective(".word", ".4byte");
@@ -156,16 +156,6 @@ class SparcAsmParser : public MCTargetAsmParser {
Sparc::I0, Sparc::I1, Sparc::I2, Sparc::I3,
Sparc::I4, Sparc::I5, Sparc::I6, Sparc::I7 };
- static const MCPhysReg FloatRegs[32] = {
- Sparc::F0, Sparc::F1, Sparc::F2, Sparc::F3,
- Sparc::F4, Sparc::F5, Sparc::F6, Sparc::F7,
- Sparc::F8, Sparc::F9, Sparc::F10, Sparc::F11,
- Sparc::F12, Sparc::F13, Sparc::F14, Sparc::F15,
- Sparc::F16, Sparc::F17, Sparc::F18, Sparc::F19,
- Sparc::F20, Sparc::F21, Sparc::F22, Sparc::F23,
- Sparc::F24, Sparc::F25, Sparc::F26, Sparc::F27,
- Sparc::F28, Sparc::F29, Sparc::F30, Sparc::F31 };
-
static const MCPhysReg DoubleRegs[32] = {
Sparc::D0, Sparc::D1, Sparc::D2, Sparc::D3,
Sparc::D4, Sparc::D5, Sparc::D6, Sparc::D7,
@@ -182,32 +172,12 @@ class SparcAsmParser : public MCTargetAsmParser {
Sparc::Q8, Sparc::Q9, Sparc::Q10, Sparc::Q11,
Sparc::Q12, Sparc::Q13, Sparc::Q14, Sparc::Q15 };
- static const MCPhysReg ASRRegs[32] = {
- SP::Y, SP::ASR1, SP::ASR2, SP::ASR3,
- SP::ASR4, SP::ASR5, SP::ASR6, SP::ASR7,
- SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11,
- SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15,
- SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19,
- SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23,
- SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27,
- SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31};
-
static const MCPhysReg IntPairRegs[] = {
Sparc::G0_G1, Sparc::G2_G3, Sparc::G4_G5, Sparc::G6_G7,
Sparc::O0_O1, Sparc::O2_O3, Sparc::O4_O5, Sparc::O6_O7,
Sparc::L0_L1, Sparc::L2_L3, Sparc::L4_L5, Sparc::L6_L7,
Sparc::I0_I1, Sparc::I2_I3, Sparc::I4_I5, Sparc::I6_I7};
- static const MCPhysReg CoprocRegs[32] = {
- Sparc::C0, Sparc::C1, Sparc::C2, Sparc::C3,
- Sparc::C4, Sparc::C5, Sparc::C6, Sparc::C7,
- Sparc::C8, Sparc::C9, Sparc::C10, Sparc::C11,
- Sparc::C12, Sparc::C13, Sparc::C14, Sparc::C15,
- Sparc::C16, Sparc::C17, Sparc::C18, Sparc::C19,
- Sparc::C20, Sparc::C21, Sparc::C22, Sparc::C23,
- Sparc::C24, Sparc::C25, Sparc::C26, Sparc::C27,
- Sparc::C28, Sparc::C29, Sparc::C30, Sparc::C31 };
-
static const MCPhysReg CoprocPairRegs[] = {
Sparc::C0_C1, Sparc::C2_C3, Sparc::C4_C5, Sparc::C6_C7,
Sparc::C8_C9, Sparc::C10_C11, Sparc::C12_C13, Sparc::C14_C15,
@@ -816,8 +786,9 @@ ParseStatus SparcAsmParser::tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
if (getLexer().getKind() != AsmToken::Percent)
return ParseStatus::NoMatch;
Parser.Lex();
- unsigned regKind = SparcOperand::rk_None;
- if (matchRegisterName(Tok, Reg, regKind)) {
+ unsigned RegKind = SparcOperand::rk_None;
+ Reg = matchRegisterName(Tok, RegKind);
+ if (Reg) {
Parser.Lex();
return ParseStatus::Success;
}
@@ -1168,14 +1139,14 @@ ParseStatus SparcAsmParser::parseOperand(OperandVector &Operands,
return ParseStatus::NoMatch;
Parser.Lex(); // eat %
- MCRegister RegNo;
unsigned RegKind;
- if (!matchRegisterName(Parser.getTok(), RegNo, RegKind))
+ MCRegister Reg = matchRegisterName(Parser.getTok(), RegKind);
+ if (!Reg)
return ParseStatus::NoMatch;
Parser.Lex(); // Eat the identifier token.
SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer()-1);
- Operands.push_back(SparcOperand::CreateReg(RegNo, RegKind, S, E));
+ Operands.push_back(SparcOperand::CreateReg(Reg, RegKind, S, E));
Res = ParseStatus::Success;
} else {
Res = parseMEMOperand(Operands);
@@ -1261,9 +1232,8 @@ SparcAsmParser::parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Op,
case AsmToken::Percent: {
Parser.Lex(); // Eat the '%'.
- MCRegister Reg;
unsigned RegKind;
- if (matchRegisterName(Parser.getTok(), Reg, RegKind)) {
+ if (MCRegister Reg = matchRegisterName(Parser.getTok(), RegKind)) {
StringRef Name = Parser.getTok().getString();
Parser.Lex(); // Eat the identifier token.
E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
@@ -1325,314 +1295,131 @@ ParseStatus SparcAsmParser::parseBranchModifiers(OperandVector &Operands) {
return ParseStatus::Success;
}
-bool SparcAsmParser::matchRegisterName(const AsmToken &Tok, MCRegister &RegNo,
- unsigned &RegKind) {
- int64_t intVal = 0;
- RegNo = 0;
- RegKind = SparcOperand::rk_None;
- if (Tok.is(AsmToken::Identifier)) {
- StringRef name = Tok.getString();
-
- // %fp
- if (name.equals("fp")) {
- RegNo = Sparc::I6;
- RegKind = SparcOperand::rk_IntReg;
- return true;
- }
- // %sp
- if (name.equals("sp")) {
- RegNo = Sparc::O6;
- RegKind = SparcOperand::rk_IntReg;
- return true;
- }
-
- if (name.equals("y")) {
- RegNo = Sparc::Y;
- RegKind = SparcOperand::rk_Special;
- return true;
- }
+#define GET_REGISTER_MATCHER
+#include "SparcGenAsmMatcher.inc"
- if (name.starts_with_insensitive("asr") &&
- !name.substr(3).getAsInteger(10, intVal) && intVal > 0 && intVal < 32) {
- RegNo = ASRRegs[intVal];
- RegKind = SparcOperand::rk_Special;
- return true;
- }
+MCRegister SparcAsmParser::matchRegisterName(const AsmToken &Tok,
+ unsigned &RegKind) {
+ RegKind = SparcOperand::rk_None;
+ if (!Tok.is(AsmToken::Identifier))
+ return SP::NoRegister;
- if (name.equals("fprs")) {
- RegNo = Sparc::ASR6;
- RegKind = SparcOperand::rk_Special;
- return true;
- }
+ StringRef Name = Tok.getString();
+ MCRegister Reg = MatchRegisterName(Name.lower());
+ if (!Reg)
+ Reg = MatchRegisterAltName(Name.lower());
- if (name.equals("icc")) {
- RegNo = Sparc::ICC;
- RegKind = SparcOperand::rk_Special;
- return true;
- }
+ if (Reg) {
+ // Some registers have identical spellings. The generated matcher might
+ // have chosen one or another spelling, e.g. "%fp" or "%i6" might have been
+ // matched to either SP::I6 or SP::I6_I7. Other parts of SparcAsmParser
+ // are not prepared for this, so we do some canonicalization.
- if (name.equals("psr")) {
- RegNo = Sparc::PSR;
+ // See the note in SparcRegisterInfo.td near ASRRegs register class.
+ if (Reg == SP::ASR4 && Name == "tick") {
RegKind = SparcOperand::rk_Special;
- return true;
+ return SP::TICK;
}
- if (name.equals("fsr")) {
- RegNo = Sparc::FSR;
- RegKind = SparcOperand::rk_Special;
- return true;
+ if (MRI.getRegClass(SP::IntRegsRegClassID).contains(Reg)) {
+ RegKind = SparcOperand::rk_IntReg;
+ return Reg;
}
-
- if (name.equals("fq")) {
- RegNo = Sparc::FQ;
- RegKind = SparcOperand::rk_Special;
- return true;
+ if (MRI.getRegClass(SP::FPRegsRegClassID).contains(Reg)) {
+ RegKind = SparcOperand::rk_FloatReg;
+ return Reg;
}
-
- if (name.equals("csr")) {
- RegNo = Sparc::CPSR;
- RegKind = SparcOperand::rk_Special;
- return true;
+ if (MRI.getRegClass(SP::CoprocRegsRegClassID).contains(Reg)) {
+ RegKind = SparcOperand::rk_CoprocReg;
+ return Reg;
}
- if (name.equals("cq")) {
- RegNo = Sparc::CPQ;
- RegKind = SparcOperand::rk_Special;
- return true;
+ // Canonicalize G0_G1 ... G30_G31 etc. to G0 ... G30.
+ if (MRI.getRegClass(SP::IntPairRegClassID).contains(Reg)) {
+ RegKind = SparcOperand::rk_IntReg;
+ return MRI.getSubReg(Reg, SP::sub_even);
}
- if (name.equals("wim")) {
- RegNo = Sparc::WIM;
- RegKind = SparcOperand::rk_Special;
- return true;
+ // Canonicalize D0 ... D15 to F0 ... F30.
+ if (MRI.getRegClass(SP::DFPRegsRegClassID).contains(Reg)) {
+ // D16 ... D31 do not have sub-registers.
+ if (MCRegister SubReg = MRI.getSubReg(Reg, SP::sub_even)) {
+ RegKind = SparcOperand::rk_FloatReg;
+ return SubReg;
+ }
+ RegKind = SparcOperand::rk_DoubleReg;
+ return Reg;
}
- if (name.equals("tbr")) {
- RegNo = Sparc::TBR;
- RegKind = SparcOperand::rk_Special;
- return true;
- }
+ // The generated matcher does not currently return QFP registers.
+ // If it changes, we will need to handle them in a similar way.
+ assert(!MRI.getRegClass(SP::QFPRegsRegClassID).contains(Reg));
- if (name.equals("xcc")) {
- // FIXME:: check 64bit.
- RegNo = Sparc::ICC;
- RegKind = SparcOperand::rk_Special;
- return true;
+ // Canonicalize C0_C1 ... C30_C31 to C0 ... C30.
+ if (MRI.getRegClass(SP::CoprocPairRegClassID).contains(Reg)) {
+ RegKind = SparcOperand::rk_CoprocReg;
+ return MRI.getSubReg(Reg, SP::sub_even);
}
- // %fcc0 - %fcc3
- if (name.starts_with_insensitive("fcc") &&
- !name.substr(3).getAsInteger(10, intVal) && intVal < 4) {
- // FIXME: check 64bit and handle %fcc1 - %fcc3
- RegNo = Sparc::FCC0 + intVal;
- RegKind = SparcOperand::rk_Special;
- return true;
- }
+ // Other registers do not need special handling.
+ RegKind = SparcOperand::rk_Special;
+ return Reg;
+ }
- // %g0 - %g7
- if (name.starts_with_insensitive("g") &&
- !name.substr(1).getAsInteger(10, intVal) && intVal < 8) {
- RegNo = IntRegs[intVal];
- RegKind = SparcOperand::rk_IntReg;
- return true;
- }
- // %o0 - %o7
- if (name.starts_with_insensitive("o") &&
- !name.substr(1).getAsInteger(10, intVal) && intVal < 8) {
- RegNo = IntRegs[8 + intVal];
- RegKind = SparcOperand::rk_IntReg;
- return true;
- }
- if (name.starts_with_insensitive("l") &&
- !name.substr(1).getAsInteger(10, intVal) && intVal < 8) {
- RegNo = IntRegs[16 + intVal];
- RegKind = SparcOperand::rk_IntReg;
- return true;
- }
- if (name.starts_with_insensitive("i") &&
- !name.substr(1).getAsInteger(10, intVal) && intVal < 8) {
- RegNo = IntRegs[24 + intVal];
- RegKind = SparcOperand::rk_IntReg;
- return true;
- }
- // %f0 - %f31
- if (name.starts_with_insensitive("f") &&
- !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 32) {
- RegNo = FloatRegs[intVal];
- RegKind = SparcOperand::rk_FloatReg;
- return true;
- }
- // %f32 - %f62
- if (name.starts_with_insensitive("f") &&
- !name.substr(1, 2).getAsInteger(10, intVal) && intVal >= 32 &&
- intVal <= 62 && (intVal % 2 == 0)) {
- // FIXME: Check V9
- RegNo = DoubleRegs[intVal/2];
- RegKind = SparcOperand::rk_DoubleReg;
- return true;
- }
+ // If we still have no match, try custom parsing.
+ // Not all registers and their spellings are modeled in td files.
- // %r0 - %r31
- if (name.starts_with_insensitive("r") &&
- !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 31) {
- RegNo = IntRegs[intVal];
- RegKind = SparcOperand::rk_IntReg;
- return true;
- }
+ // %r0 - %r31
+ int64_t RegNo = 0;
+ if (Name.starts_with_insensitive("r") &&
+ !Name.substr(1, 2).getAsInteger(10, RegNo) && RegNo < 31) {
+ RegKind = SparcOperand::rk_IntReg;
+ return IntRegs[RegNo];
+ }
- // %c0 - %c31
- if (name.starts_with_insensitive("c") &&
- !name.substr(1).getAsInteger(10, intVal) && intVal < 32) {
- RegNo = CoprocRegs[intVal];
- RegKind = SparcOperand::rk_CoprocReg;
- return true;
- }
+ if (Name.equals("xcc")) {
+ // FIXME:: check 64bit.
+ RegKind = SparcOperand::rk_Special;
+ return SP::ICC;
+ }
- if (name.equals("tpc")) {
- RegNo = Sparc::TPC;
- RegKind = SparcOperand::rk_Special;
- return true;
- }
- if (name.equals("tnpc")) {
- RegNo = Sparc::TNPC;
- RegKind = SparcOperand::rk_Special;
- return true;
- }
- if (name.equals("tstate")) {
- RegNo = Sparc::TSTATE;
- RegKind = SparcOperand::rk_Special;
- return true;
- }
- if (name.equals("tt")) {
- RegNo = Sparc::TT;
- RegKind = SparcOperand::rk_Special;
- return true;
- }
- if (name.equals("tick")) {
- RegNo = Sparc::TICK;
- RegKind = SparcOperand::rk_Special;
- return true;
- }
- if (name.equals("tba")) {
- RegNo = Sparc::TBA;
- RegKind = SparcOperand::rk_Special;
- return true;
- }
- if (name.equals("pstate")) {
- RegNo = Sparc::PSTATE;
- RegKind = SparcOperand::rk_Special;
- return true;
- }
- if (name.equals("tl")) {
- RegNo = Sparc::TL;
- RegKind = SparcOperand::rk_Special;
- return true;
- }
- if (name.equals("pil")) {
- RegNo = Sparc::PIL;
- RegKind = SparcOperand::rk_Special;
- return true;
- }
- if (name.equals("cwp")) {
- RegNo = Sparc::CWP;
- RegKind = SparcOperand::rk_Special;
- return true;
- }
- if (name.equals("cansave")) {
- RegNo = Sparc::CANSAVE;
- RegKind = SparcOperand::rk_Special;
- return true;
- }
- if (name.equals("canrestore")) {
- RegNo = Sparc::CANRESTORE;
- RegKind = SparcOperand::rk_Special;
- return true;
- }
- if (name.equals("cleanwin")) {
- RegNo = Sparc::CLEANWIN;
- RegKind = SparcOperand::rk_Special;
- return true;
- }
- if (name.equals("otherwin")) {
- RegNo = Sparc::OTHERWIN;
- RegKind = SparcOperand::rk_Special;
- return true;
- }
- if (name.equals("wstate")) {
- RegNo = Sparc::WSTATE;
- RegKind = SparcOperand::rk_Special;
- return true;
- }
- if (name.equals("pc")) {
- RegNo = Sparc::ASR5;
- RegKind = SparcOperand::rk_Special;
- return true;
- }
- if (name.equals("asi")) {
- RegNo = Sparc::ASR3;
- RegKind = SparcOperand::rk_Special;
- return true;
- }
- if (name.equals("ccr")) {
- RegNo = Sparc::ASR2;
- RegKind = SparcOperand::rk_Special;
- return true;
- }
- if (name.equals("gl")) {
- RegNo = Sparc::GL;
- RegKind = SparcOperand::rk_Special;
- return true;
- }
- if (name.equals("ver")) {
- RegNo = Sparc::VER;
- RegKind = SparcOperand::rk_Special;
- return true;
- }
+ // JPS1 extension - aliases for ASRs
+ // Section A.51 - Read State Register
+ if (Name.equals("pcr")) {
+ RegKind = SparcOperand::rk_Special;
+ return SP::ASR16;
+ }
- // JPS1 extension - aliases for ASRs
- // Section A.51 - Read State Register
- if (name.equals("pcr")) {
- RegNo = Sparc::ASR16;
- RegKind = SparcOperand::rk_Special;
- return true;
- }
- if (name.equals("pic")) {
- RegNo = Sparc::ASR17;
- RegKind = SparcOperand::rk_Special;
- return true;
- }
- if (name.equals("dcr")) {
- RegNo = Sparc::ASR18;
- RegKind = SparcOperand::rk_Special;
- return true;
- }
- if (name.equals("gsr")) {
- RegNo = Sparc::ASR19;
- RegKind = SparcOperand::rk_Special;
- return true;
- }
- if (name.equals("softint")) {
- RegNo = Sparc::ASR22;
- RegKind = SparcOperand::rk_Special;
- return true;
- }
- if (name.equals("tick_cmpr")) {
- RegNo = Sparc::ASR23;
- RegKind = SparcOperand::rk_Special;
- return true;
- }
- if (name.equals("stick") || name.equals("sys_tick")) {
- RegNo = Sparc::ASR24;
- RegKind = SparcOperand::rk_Special;
- return true;
- }
- if (name.equals("stick_cmpr") || name.equals("sys_tick_cmpr")) {
- RegNo = Sparc::ASR25;
- RegKind = SparcOperand::rk_Special;
- return true;
- }
+ if (Name.equals("pic")) {
+ RegKind = SparcOperand::rk_Special;
+ return SP::ASR17;
}
- return false;
+ if (Name.equals("dcr")) {
+ RegKind = SparcOperand::rk_Special;
+ return SP::ASR18;
+ }
+ if (Name.equals("gsr")) {
+ RegKind = SparcOperand::rk_Special;
+ return SP::ASR19;
+ }
+ if (Name.equals("softint")) {
+ RegKind = SparcOperand::rk_Special;
+ return SP::ASR22;
+ }
+ if (Name.equals("tick_cmpr")) {
+ RegKind = SparcOperand::rk_Special;
+ return SP::ASR23;
+ }
+ if (Name.equals("stick") || Name.equals("sys_tick")) {
+ RegKind = SparcOperand::rk_Special;
+ return SP::ASR24;
+ }
+ if (Name.equals("stick_cmpr") || Name.equals("sys_tick_cmpr")) {
+ RegKind = SparcOperand::rk_Special;
+ return SP::ASR25;
+ }
+
+ return SP::NoRegister;
}
// Determine if an expression contains a reference to the symbol
@@ -1737,7 +1524,6 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSparcAsmParser() {
RegisterMCAsmParser<SparcAsmParser> C(getTheSparcelTarget());
}
-#define GET_REGISTER_MATCHER
#define GET_MATCHER_IMPLEMENTATION
#include "SparcGenAsmMatcher.inc"
diff --git a/llvm/lib/Target/Sparc/Sparc.td b/llvm/lib/Target/Sparc/Sparc.td
index 38a59e650f33c7..45cf985cfa0627 100644
--- a/llvm/lib/Target/Sparc/Sparc.td
+++ b/llvm/lib/Target/Sparc/Sparc.td
@@ -99,7 +99,8 @@ include "SparcInstrInfo.td"
def SparcInstrInfo : InstrInfo;
def SparcAsmParser : AsmParser {
- bit ShouldEmitMatchRegisterName = 0;
+ let ShouldEmitMatchRegisterAltName = true;
+ let AllowDuplicateRegisterNames = true;
}
def SparcAsmParserVariant : AsmParserVariant {
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