[llvm] AMDGPU/GlobalISel: Uniformity info based regbankselect (PR #73684)

[Petar Avramovic via llvm-commits]

petar-avramovic wrote:

I will probably have to search for another opcode or not support gfx12 as this patch leaves regbankselect in semi-broken state.
The problem is when you have uniform G_FADD but uniform inputs come in vgprs (not sgpr) because opcode that provides input did not insert readfirstlane. This creates vgpr to sgpr copies.

In the meantime, as a remainder, here is a summary of this and upcoming patches:
go through defs of all instructions and use machine-uniformity-analysis to pre-assign reg-banks on each register: 
- `uniform->sgpr`
- `divergent->vgpr`

Reg-bank-select does **not** change pre-assigned reg-banks on registers. Based on available instructions it can allocate additional registers and insert copies and readfirstlanes.
Essentially if there is no available SALU machine instruction to select `generic opcode` with `pre-assigned sgpr operands`
Reg-bank-select  will create `new vgpr operands` for each operand where:
- `pre-assigned sgpr operands` will be replaced with `new vgpr operands` 
- `pre-assigned input sgpr operands` will be copied to `new input vgpr operands`  
- `new output vgpr operand` will readfirstlane into `pre-assigned output sgpr operand`

Do you agree with the approach in general?

Later there are options for optimizations. 
First combine away `readfirstlane` + `sgpr to vgpr copy`. This will leave us with using maximum possible number of sgprs. 
Then consider moving-to-VALU.

https://github.com/llvm/llvm-project/pull/73684