[llvm] [BOLT][AArch64] Fixes assertion errors occurred when perf2bolt was executed (PR #83394)

via llvm-commits llvm-commits at lists.llvm.org
Thu Feb 29 01:21:43 PST 2024


github-actions[bot] wrote:

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git-clang-format --diff d1a461dbb2293d9258d400b5426f610bb5191228 dba9931affd933332623d9d63d799e4c28c40b60 -- bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
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View the diff from clang-format here.
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diff --git a/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp b/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
index 677e11e37d..7506bb49dc 100644
--- a/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
+++ b/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
@@ -708,13 +708,13 @@ public:
     AArch64_AM::ShiftExtendType ExtendType =
         AArch64_AM::getArithExtendType(OperandExtension);
     if (ShiftVal != 2) {
-       // In this case the left shift amount is zero.
-       // The range could be 0 to 4.
-       //   adr     x6, 0x219fb0 <sigall_set+0x88>
-       //   add     x6, x6, x14, lsl #2
-       //   ldr     w7, [x6]
-       //   add     x6, x6, w7, sxtw => no shift amount
-       //   br      x6
+      // In this case the left shift amount is zero.
+      // The range could be 0 to 4.
+      //   adr     x6, 0x219fb0 <sigall_set+0x88>
+      //   add     x6, x6, x14, lsl #2
+      //   ldr     w7, [x6]
+      //   add     x6, x6, w7, sxtw => no shift amount
+      //   br      x6
       return false;
     }
 

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https://github.com/llvm/llvm-project/pull/83394


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