[llvm] [Hexagon] Update the debug instruction call. (PR #83372)

[Sumanth Gundapaneni via llvm-commits]

https://github.com/sgundapa created https://github.com/llvm/llvm-project/pull/83372

None

>From 2a89fe144126959f60feb3e2c89aad54cd6ed569 Mon Sep 17 00:00:00 2001
From: Sumanth Gundapaneni <sgundapa at quicinc.com>
Date: Wed, 28 Feb 2024 19:42:20 -0800
Subject: [PATCH] [Hexagon] Update the debug instruction call.

---
 llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp    | 4 ++--
 llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
index 3b8234c0118435..4b3b0142cc186a 100644
--- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
@@ -1002,8 +1002,8 @@ namespace {
 bool DeadCodeElimination::isDead(unsigned R) const {
   for (const MachineOperand &MO : MRI.use_operands(R)) {
     const MachineInstr *UseI = MO.getParent();
-    if (UseI->isDebugValue())
-      continue;
+    if (UseI->isDebugInstr())
+        continue;
     if (UseI->isPHI()) {
       assert(!UseI->getOperand(0).getSubReg());
       Register DR = UseI->getOperand(0).getReg();
diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
index e38c8bacaf2bab..56472d633694ae 100644
--- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
@@ -1180,7 +1180,7 @@ void HexagonPacketizerList::unpacketizeSoloInstrs(MachineFunction &MF) {
       bool InsertBeforeBundle;
       if (MI.isInlineAsm())
         InsertBeforeBundle = !hasWriteToReadDep(MI, *BundleIt, HRI);
-      else if (MI.isDebugValue())
+      else if (MI.isDebugInstr())
         InsertBeforeBundle = true;
       else
         continue;