[llvm] Imprecise switch case (PR #82795)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 27 22:05:23 PST 2024
================
@@ -0,0 +1,312 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -passes=simplifycfg -switch-to-select < %s | FileCheck -check-prefix=ALL %s
+
+
+define float @SimpleTestTwoCasesAndDefault(<2 x float> noundef %PerspInterpCenter, i32 inreg noundef %PrimMask) {
+; ALL-LABEL: @SimpleTestTwoCasesAndDefault(
+; ALL-NEXT: .entry:
+; ALL-NEXT: [[PERSPINTERPCENTER_I1:%.*]] = extractelement <2 x float> [[PERSPINTERPCENTER:%.*]], i64 1
+; ALL-NEXT: [[PERSPINTERPCENTER_I0:%.*]] = extractelement <2 x float> [[PERSPINTERPCENTER]], i64 0
+; ALL-NEXT: [[TMP0:%.*]] = call float @llvm.amdgcn.interp.p1(float [[PERSPINTERPCENTER_I0]], i32 immarg 1, i32 immarg 0, i32 [[PRIMMASK:%.*]])
+; ALL-NEXT: [[TMP1:%.*]] = call float @llvm.amdgcn.interp.p2(float [[TMP0]], float [[PERSPINTERPCENTER_I1]], i32 immarg 1, i32 immarg 0, i32 [[PRIMMASK]])
+; ALL-NEXT: [[TMP2:%.*]] = fmul reassoc nnan nsz arcp contract afn float [[TMP1]], 3.000000e+00
+; ALL-NEXT: [[TMP3:%.*]] = call reassoc nnan nsz arcp contract afn float @llvm.floor.f32(float [[TMP2]])
+; ALL-NEXT: [[TMP4:%.*]] = fptosi float [[TMP3]] to i32
+; ALL-NEXT: [[DOTFR:%.*]] = freeze i32 [[TMP4]]
+; ALL-NEXT: [[TMP5:%.*]] = icmp eq i32 [[DOTFR]], 1
+; ALL-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP12:%.*]]
+; ALL: 6:
+; ALL-NEXT: [[TMP7:%.*]] = call float @llvm.amdgcn.interp.p1(float [[PERSPINTERPCENTER_I0]], i32 immarg 0, i32 immarg 0, i32 [[PRIMMASK]])
+; ALL-NEXT: [[TMP8:%.*]] = call float @llvm.amdgcn.interp.p2(float [[TMP7]], float [[PERSPINTERPCENTER_I1]], i32 immarg 0, i32 immarg 0, i32 [[PRIMMASK]])
+; ALL-NEXT: [[TMP9:%.*]] = fmul reassoc nnan nsz arcp contract afn float [[TMP8]], 4.000000e+00
+; ALL-NEXT: [[TMP10:%.*]] = call reassoc nnan nsz arcp contract afn float @llvm.floor.f32(float [[TMP9]])
+; ALL-NEXT: [[TMP11:%.*]] = fptosi float [[TMP10]] to i32
+; ALL-NEXT: [[COND_FREEZE1:%.*]] = freeze i32 [[TMP11]]
+; ALL-NEXT: [[SWITCH_SELECTCMP:%.*]] = icmp eq i32 [[COND_FREEZE1]], 1
+; ALL-NEXT: [[SWITCH_SELECT:%.*]] = select i1 [[SWITCH_SELECTCMP]], float 2.000000e+00, float 4.000000e+00
+; ALL-NEXT: [[SWITCH_SELECTCMP1:%.*]] = icmp eq i32 [[COND_FREEZE1]], 0
+; ALL-NEXT: [[SWITCH_SELECT2:%.*]] = select i1 [[SWITCH_SELECTCMP1]], float 1.000000e+00, float [[SWITCH_SELECT]]
+; ALL-NEXT: br label [[TMP12]]
+; ALL: 12:
+; ALL-NEXT: [[SAMPLEPOS_1_I0:%.*]] = phi float [ 0.000000e+00, [[DOTENTRY:%.*]] ], [ [[SWITCH_SELECT2]], [[TMP6]] ]
+; ALL-NEXT: ret float [[SAMPLEPOS_1_I0]]
+;
+.entry:
+ %PerspInterpCenter.i1 = extractelement <2 x float> %PerspInterpCenter, i64 1
+ %PerspInterpCenter.i0 = extractelement <2 x float> %PerspInterpCenter, i64 0
+ %0 = call float @llvm.amdgcn.interp.p1(float %PerspInterpCenter.i0, i32 immarg 1, i32 immarg 0, i32 %PrimMask) #1
+ %1 = call float @llvm.amdgcn.interp.p2(float %0, float %PerspInterpCenter.i1, i32 immarg 1, i32 immarg 0, i32 %PrimMask) #1
+ %2 = fmul reassoc nnan nsz arcp contract afn float %1, 3.000000e00
+ %3 = call reassoc nnan nsz arcp contract afn float @llvm.floor.f32(float %2)
+ %4 = fptosi float %3 to i32
+ %.fr = freeze i32 %4
+ %5 = icmp eq i32 %.fr, 1
+ br i1 %5, label %6, label %14
+
+6: ; preds = %.entry
+ %7 = call float @llvm.amdgcn.interp.p1(float %PerspInterpCenter.i0, i32 immarg 0, i32 immarg 0, i32 %PrimMask) #1
+ %8 = call float @llvm.amdgcn.interp.p2(float %7, float %PerspInterpCenter.i1, i32 immarg 0, i32 immarg 0, i32 %PrimMask) #1
+ %9 = fmul reassoc nnan nsz arcp contract afn float %8, 4.000000e00
+ %10 = call reassoc nnan nsz arcp contract afn float @llvm.floor.f32(float %9)
+ %11 = fptosi float %10 to i32
+ %cond.freeze1 = freeze i32 %11
+ switch i32 %cond.freeze1, label %14 [
+ i32 0, label %12
+ i32 1, label %13
+ ]
+
+12: ; preds = %6
+ br label %14
+
+13: ; preds = %6
+ br label %14
+
+14: ; preds = %12, %13, %6, %.entry
+ %samplePos.1.i0 = phi float [ 0.000000e00, %.entry ], [ 2.000000e00, %13 ], [ 1.000000e00, %12 ], [ 4.000000e00, %6 ]
+ ret float %samplePos.1.i0
+}
+
+define float @SimpleTestTwoCases(<2 x float> noundef %PerspInterpCenter, i32 inreg noundef %PrimMask) {
+; ALL-LABEL: @SimpleTestTwoCases(
+; ALL-NEXT: .entry:
+; ALL-NEXT: [[PERSPINTERPCENTER_I1:%.*]] = extractelement <2 x float> [[PERSPINTERPCENTER:%.*]], i64 1
+; ALL-NEXT: [[PERSPINTERPCENTER_I0:%.*]] = extractelement <2 x float> [[PERSPINTERPCENTER]], i64 0
+; ALL-NEXT: [[TMP0:%.*]] = call float @llvm.amdgcn.interp.p1(float [[PERSPINTERPCENTER_I0]], i32 immarg 1, i32 immarg 0, i32 [[PRIMMASK:%.*]])
+; ALL-NEXT: [[TMP1:%.*]] = call float @llvm.amdgcn.interp.p2(float [[TMP0]], float [[PERSPINTERPCENTER_I1]], i32 immarg 1, i32 immarg 0, i32 [[PRIMMASK]])
+; ALL-NEXT: [[TMP2:%.*]] = fmul reassoc nnan nsz arcp contract afn float [[TMP1]], 3.000000e+00
+; ALL-NEXT: [[TMP3:%.*]] = call reassoc nnan nsz arcp contract afn float @llvm.floor.f32(float [[TMP2]])
+; ALL-NEXT: [[TMP4:%.*]] = fptosi float [[TMP3]] to i32
+; ALL-NEXT: [[DOTFR:%.*]] = freeze i32 [[TMP4]]
+; ALL-NEXT: [[TMP5:%.*]] = icmp eq i32 [[DOTFR]], 1
+; ALL-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP12:%.*]]
+; ALL: 6:
+; ALL-NEXT: [[TMP7:%.*]] = call float @llvm.amdgcn.interp.p1(float [[PERSPINTERPCENTER_I0]], i32 immarg 0, i32 immarg 0, i32 [[PRIMMASK]])
+; ALL-NEXT: [[TMP8:%.*]] = call float @llvm.amdgcn.interp.p2(float [[TMP7]], float [[PERSPINTERPCENTER_I1]], i32 immarg 0, i32 immarg 0, i32 [[PRIMMASK]])
+; ALL-NEXT: [[TMP9:%.*]] = fmul reassoc nnan nsz arcp contract afn float [[TMP8]], 4.000000e+00
+; ALL-NEXT: [[TMP10:%.*]] = call reassoc nnan nsz arcp contract afn float @llvm.floor.f32(float [[TMP9]])
+; ALL-NEXT: [[TMP11:%.*]] = fptosi float [[TMP10]] to i32
+; ALL-NEXT: [[COND_FREEZE1:%.*]] = freeze i32 [[TMP11]]
+; ALL-NEXT: [[SWITCH_SELECTCMP:%.*]] = icmp eq i32 [[COND_FREEZE1]], 1
+; ALL-NEXT: [[SWITCH_SELECT:%.*]] = select i1 [[SWITCH_SELECTCMP]], float 2.000000e+00, float 0.000000e+00
+; ALL-NEXT: [[SWITCH_SELECTCMP1:%.*]] = icmp eq i32 [[COND_FREEZE1]], 0
+; ALL-NEXT: [[SWITCH_SELECT2:%.*]] = select i1 [[SWITCH_SELECTCMP1]], float 1.000000e+00, float [[SWITCH_SELECT]]
+; ALL-NEXT: br label [[TMP12]]
+; ALL: 12:
+; ALL-NEXT: [[SAMPLEPOS_1_I0:%.*]] = phi float [ 0.000000e+00, [[DOTENTRY:%.*]] ], [ [[SWITCH_SELECT2]], [[TMP6]] ]
+; ALL-NEXT: ret float [[SAMPLEPOS_1_I0]]
+;
+.entry:
+ %PerspInterpCenter.i1 = extractelement <2 x float> %PerspInterpCenter, i64 1
+ %PerspInterpCenter.i0 = extractelement <2 x float> %PerspInterpCenter, i64 0
+ %0 = call float @llvm.amdgcn.interp.p1(float %PerspInterpCenter.i0, i32 immarg 1, i32 immarg 0, i32 %PrimMask) #1
+ %1 = call float @llvm.amdgcn.interp.p2(float %0, float %PerspInterpCenter.i1, i32 immarg 1, i32 immarg 0, i32 %PrimMask) #1
+ %2 = fmul reassoc nnan nsz arcp contract afn float %1, 3.000000e00
+ %3 = call reassoc nnan nsz arcp contract afn float @llvm.floor.f32(float %2)
+ %4 = fptosi float %3 to i32
+ %.fr = freeze i32 %4
+ %5 = icmp eq i32 %.fr, 1
+ br i1 %5, label %6, label %14
+
+6: ; preds = %.entry
+ %7 = call float @llvm.amdgcn.interp.p1(float %PerspInterpCenter.i0, i32 immarg 0, i32 immarg 0, i32 %PrimMask) #1
+ %8 = call float @llvm.amdgcn.interp.p2(float %7, float %PerspInterpCenter.i1, i32 immarg 0, i32 immarg 0, i32 %PrimMask) #1
+ %9 = fmul reassoc nnan nsz arcp contract afn float %8, 4.000000e00
+ %10 = call reassoc nnan nsz arcp contract afn float @llvm.floor.f32(float %9)
+ %11 = fptosi float %10 to i32
+ %cond.freeze1 = freeze i32 %11
+ switch i32 %cond.freeze1, label %14 [
+ i32 0, label %12
+ i32 1, label %13
+ ]
+
+12: ; preds = %6
+ br label %14
+
+13: ; preds = %6
+ br label %14
+
+14: ; preds = %6, %12, %13, %.entry
+ %samplePos.1.i0 = phi float [ 0.000000e00, %.entry ], [ 0.000000e00, %6 ], [ 2.000000e00, %13 ], [ 1.000000e00, %12 ]
+ ret float %samplePos.1.i0
+}
+
+
+
+define float @SimpleTestSwitch(<2 x float> noundef %PerspInterpCenter, i32 inreg noundef %PrimMask) {
+; ALL-LABEL: @SimpleTestSwitch(
+; ALL-NEXT: .entry:
+; ALL-NEXT: [[PERSPINTERPCENTER_I1:%.*]] = extractelement <2 x float> [[PERSPINTERPCENTER:%.*]], i64 1
+; ALL-NEXT: [[PERSPINTERPCENTER_I0:%.*]] = extractelement <2 x float> [[PERSPINTERPCENTER]], i64 0
+; ALL-NEXT: [[TMP0:%.*]] = call float @llvm.amdgcn.interp.p1(float [[PERSPINTERPCENTER_I0]], i32 immarg 1, i32 immarg 0, i32 [[PRIMMASK:%.*]])
+; ALL-NEXT: [[TMP1:%.*]] = call float @llvm.amdgcn.interp.p2(float [[TMP0]], float [[PERSPINTERPCENTER_I1]], i32 immarg 1, i32 immarg 0, i32 [[PRIMMASK]])
+; ALL-NEXT: [[TMP2:%.*]] = fmul reassoc nnan nsz arcp contract afn float [[TMP1]], 3.000000e+00
+; ALL-NEXT: [[TMP3:%.*]] = call reassoc nnan nsz arcp contract afn float @llvm.floor.f32(float [[TMP2]])
+; ALL-NEXT: [[TMP4:%.*]] = fptosi float [[TMP3]] to i32
+; ALL-NEXT: [[DOTFR:%.*]] = freeze i32 [[TMP4]]
+; ALL-NEXT: [[TMP5:%.*]] = icmp eq i32 [[DOTFR]], 1
+; ALL-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP12:%.*]]
+; ALL: 6:
+; ALL-NEXT: [[TMP7:%.*]] = call float @llvm.amdgcn.interp.p1(float [[PERSPINTERPCENTER_I0]], i32 immarg 0, i32 immarg 0, i32 [[PRIMMASK]])
+; ALL-NEXT: [[TMP8:%.*]] = call float @llvm.amdgcn.interp.p2(float [[TMP7]], float [[PERSPINTERPCENTER_I1]], i32 immarg 0, i32 immarg 0, i32 [[PRIMMASK]])
+; ALL-NEXT: [[TMP9:%.*]] = fmul reassoc nnan nsz arcp contract afn float [[TMP8]], 4.000000e+00
+; ALL-NEXT: [[TMP10:%.*]] = call reassoc nnan nsz arcp contract afn float @llvm.floor.f32(float [[TMP9]])
+; ALL-NEXT: [[TMP11:%.*]] = fptosi float [[TMP10]] to i32
+; ALL-NEXT: [[COND_FREEZE1:%.*]] = freeze i32 [[TMP11]]
+; ALL-NEXT: [[SWITCH_SELECTCMP:%.*]] = icmp eq i32 [[COND_FREEZE1]], 0
+; ALL-NEXT: [[SWITCH_SELECTCMP1:%.*]] = icmp eq i32 [[COND_FREEZE1]], 1
+; ALL-NEXT: [[SWITCH_SELECTCMP2:%.*]] = icmp eq i32 [[COND_FREEZE1]], 2
+; ALL-NEXT: [[SWITCH_SELECTCMP3:%.*]] = icmp eq i32 [[COND_FREEZE1]], 3
+; ALL-NEXT: [[SWITCHACIM_SELECT:%.*]] = select i1 [[SWITCH_SELECTCMP3]], float 4.000000e+00, float 0.000000e+00
+; ALL-NEXT: [[SWITCHACIM_SELECT4:%.*]] = select i1 [[SWITCH_SELECTCMP2]], float 3.000000e+00, float [[SWITCHACIM_SELECT]]
+; ALL-NEXT: [[SWITCHACIM_SELECT5:%.*]] = select i1 [[SWITCH_SELECTCMP1]], float 2.000000e+00, float [[SWITCHACIM_SELECT4]]
+; ALL-NEXT: [[SWITCHACIM_SELECT6:%.*]] = select i1 [[SWITCH_SELECTCMP]], float 1.000000e+00, float [[SWITCHACIM_SELECT5]]
+; ALL-NEXT: br label [[TMP12]]
+; ALL: 12:
+; ALL-NEXT: [[SAMPLEPOS_1_I0:%.*]] = phi float [ 0.000000e+00, [[DOTENTRY:%.*]] ], [ [[SWITCHACIM_SELECT6]], [[TMP6]] ]
+; ALL-NEXT: ret float [[SAMPLEPOS_1_I0]]
+;
+.entry:
+ %PerspInterpCenter.i1 = extractelement <2 x float> %PerspInterpCenter, i64 1
+ %PerspInterpCenter.i0 = extractelement <2 x float> %PerspInterpCenter, i64 0
+ %0 = call float @llvm.amdgcn.interp.p1(float %PerspInterpCenter.i0, i32 immarg 1, i32 immarg 0, i32 %PrimMask) #1
+ %1 = call float @llvm.amdgcn.interp.p2(float %0, float %PerspInterpCenter.i1, i32 immarg 1, i32 immarg 0, i32 %PrimMask) #1
+ %2 = fmul reassoc nnan nsz arcp contract afn float %1, 3.000000e00
+ %3 = call reassoc nnan nsz arcp contract afn float @llvm.floor.f32(float %2)
+ %4 = fptosi float %3 to i32
+ %.fr = freeze i32 %4
+ %5 = icmp eq i32 %.fr, 1
+ br i1 %5, label %6, label %16
+
+6: ; preds = %.entry
+ %7 = call float @llvm.amdgcn.interp.p1(float %PerspInterpCenter.i0, i32 immarg 0, i32 immarg 0, i32 %PrimMask) #1
+ %8 = call float @llvm.amdgcn.interp.p2(float %7, float %PerspInterpCenter.i1, i32 immarg 0, i32 immarg 0, i32 %PrimMask) #1
+ %9 = fmul reassoc nnan nsz arcp contract afn float %8, 4.000000e00
+ %10 = call reassoc nnan nsz arcp contract afn float @llvm.floor.f32(float %9)
+ %11 = fptosi float %10 to i32
+ %cond.freeze1 = freeze i32 %11
+ switch i32 %cond.freeze1, label %16 [
+ i32 0, label %12
+ i32 1, label %13
+ i32 2, label %14
+ i32 3, label %15
+ ]
+
+12: ; preds = %6
+ br label %16
+
+13: ; preds = %6
+ br label %16
+
+14: ; preds = %6
+ br label %16
+
+15: ; preds = %6
+ br label %16
+
+16: ; preds = %6, %12, %13, %14, %15, %.entry
+ %samplePos.1.i0 = phi float [ 0.000000e00, %.entry ], [ 0.000000e00, %6 ], [ 4.000000e00, %15 ], [ 3.000000e00, %14 ], [ 2.000000e00, %13 ], [ 1.000000e00, %12 ]
+ ret float %samplePos.1.i0
+}
+
+define float @LittleMoreComplexSwitch(<2 x float> noundef %PerspInterpCenter, i32 inreg noundef %PrimMask) {
+; ALL-LABEL: @LittleMoreComplexSwitch(
+; ALL-NEXT: .entry:
+; ALL-NEXT: [[PERSPINTERPCENTER_I1:%.*]] = extractelement <2 x float> [[PERSPINTERPCENTER:%.*]], i64 1
+; ALL-NEXT: [[PERSPINTERPCENTER_I0:%.*]] = extractelement <2 x float> [[PERSPINTERPCENTER]], i64 0
+; ALL-NEXT: [[TMP0:%.*]] = call float @llvm.amdgcn.interp.p1(float [[PERSPINTERPCENTER_I0]], i32 immarg 1, i32 immarg 0, i32 [[PRIMMASK:%.*]])
+; ALL-NEXT: [[TMP1:%.*]] = call float @llvm.amdgcn.interp.p2(float [[TMP0]], float [[PERSPINTERPCENTER_I1]], i32 immarg 1, i32 immarg 0, i32 [[PRIMMASK]])
+; ALL-NEXT: [[TMP2:%.*]] = fmul reassoc nnan nsz arcp contract afn float [[TMP1]], 3.000000e+00
+; ALL-NEXT: [[TMP3:%.*]] = call reassoc nnan nsz arcp contract afn float @llvm.floor.f32(float [[TMP2]])
+; ALL-NEXT: [[TMP4:%.*]] = fptosi float [[TMP3]] to i32
+; ALL-NEXT: [[DOTFR:%.*]] = freeze i32 [[TMP4]]
+; ALL-NEXT: [[TMP5:%.*]] = icmp eq i32 [[DOTFR]], 1
+; ALL-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP21:%.*]]
+; ALL: 6:
+; ALL-NEXT: [[TMP7:%.*]] = call float @llvm.amdgcn.interp.p1(float [[PERSPINTERPCENTER_I0]], i32 immarg 0, i32 immarg 0, i32 [[PRIMMASK]])
+; ALL-NEXT: [[TMP8:%.*]] = call float @llvm.amdgcn.interp.p2(float [[TMP7]], float [[PERSPINTERPCENTER_I1]], i32 immarg 0, i32 immarg 0, i32 [[PRIMMASK]])
+; ALL-NEXT: [[TMP9:%.*]] = fmul reassoc nnan nsz arcp contract afn float [[TMP8]], 4.000000e+00
+; ALL-NEXT: [[TMP10:%.*]] = call reassoc nnan nsz arcp contract afn float @llvm.floor.f32(float [[TMP9]])
+; ALL-NEXT: [[TMP11:%.*]] = fptosi float [[TMP10]] to i32
+; ALL-NEXT: [[COND_FREEZE1:%.*]] = freeze i32 [[TMP11]]
+; ALL-NEXT: [[TMP12:%.*]] = sitofp i32 [[COND_FREEZE1]] to float
+; ALL-NEXT: [[TMP13:%.*]] = fsub reassoc nnan nsz arcp contract afn float [[TMP9]], [[TMP12]]
+; ALL-NEXT: [[SCALE_I0:%.*]] = fmul reassoc nnan nsz arcp contract afn float [[TMP13]], 2.000000e+00
+; ALL-NEXT: [[TMP14:%.*]] = fmul reassoc nnan nsz arcp contract afn float [[TMP1]], 6.000000e+00
+; ALL-NEXT: [[DOTI0:%.*]] = fadd reassoc nnan nsz arcp contract afn float [[SCALE_I0]], -1.000000e+00
+; ALL-NEXT: [[DOTI1:%.*]] = fadd reassoc nnan nsz arcp contract afn float [[TMP14]], -3.000000e+00
+; ALL-NEXT: switch i32 [[COND_FREEZE1]], label [[TMP21]] [
+; ALL-NEXT: i32 0, label [[TMP15:%.*]]
+; ALL-NEXT: i32 1, label [[TMP16:%.*]]
+; ALL-NEXT: i32 2, label [[TMP17:%.*]]
+; ALL-NEXT: i32 3, label [[TMP19:%.*]]
+; ALL-NEXT: ]
+; ALL: 15:
+; ALL-NEXT: br label [[TMP21]]
+; ALL: 16:
+; ALL-NEXT: br label [[TMP21]]
+; ALL: 17:
+; ALL-NEXT: [[TMP18:%.*]] = fneg reassoc nnan nsz arcp contract afn float [[DOTI0]]
+; ALL-NEXT: br label [[TMP21]]
+; ALL: 19:
+; ALL-NEXT: [[TMP20:%.*]] = fneg reassoc nnan nsz arcp contract afn float [[DOTI0]]
+; ALL-NEXT: br label [[TMP21]]
+; ALL: 21:
+; ALL-NEXT: [[SAMPLEPOS_1_I0:%.*]] = phi float [ 0.000000e+00, [[DOTENTRY:%.*]] ], [ 0.000000e+00, [[TMP6]] ], [ [[TMP20]], [[TMP19]] ], [ 1.000000e+00, [[TMP17]] ], [ [[DOTI0]], [[TMP16]] ], [ 1.000000e+00, [[TMP15]] ]
+; ALL-NEXT: [[SAMPLEPOS_1_I1:%.*]] = phi float [ 0.000000e+00, [[DOTENTRY]] ], [ 0.000000e+00, [[TMP6]] ], [ [[DOTI1]], [[TMP19]] ], [ [[DOTI1]], [[TMP17]] ], [ [[DOTI1]], [[TMP16]] ], [ 1.000000e+00, [[TMP15]] ]
+; ALL-NEXT: [[SAMPLEPOS_1_I2:%.*]] = phi float [ 0.000000e+00, [[DOTENTRY]] ], [ 0.000000e+00, [[TMP6]] ], [ -1.000000e+00, [[TMP19]] ], [ [[TMP18]], [[TMP17]] ], [ 1.000000e+00, [[TMP16]] ], [ 1.000000e+00, [[TMP15]] ]
+; ALL-NEXT: [[TMP22:%.*]] = call reassoc nnan nsz arcp contract afn float @llvm.amdgcn.cubesc(float [[SAMPLEPOS_1_I0]], float [[SAMPLEPOS_1_I1]], float [[SAMPLEPOS_1_I2]])
+; ALL-NEXT: ret float [[TMP22]]
+;
+ .entry:
+ %PerspInterpCenter.i1 = extractelement <2 x float> %PerspInterpCenter, i64 1
+ %PerspInterpCenter.i0 = extractelement <2 x float> %PerspInterpCenter, i64 0
+ %0 = call float @llvm.amdgcn.interp.p1(float %PerspInterpCenter.i0, i32 immarg 1, i32 immarg 0, i32 %PrimMask) #1
----------------
arsenm wrote:
Use named values in tests
https://github.com/llvm/llvm-project/pull/82795
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