[llvm] [RISCV] Move RISCVVType namespace to Support (PR #83222)
Wang Pengcheng via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 27 21:24:02 PST 2024
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/83222
>From f11ed8e28162e8fb87beaffdc0ccac143fab1291 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: Wed, 28 Feb 2024 13:23:04 +0800
Subject: [PATCH] [RISCV] Move RISCVVType namespace to TargetParser
Clang and some middle-end optimizations may need these helper
functions.
This can reduce some duplications.
---
.../llvm/TargetParser/RISCVTargetParser.h | 77 ++++++++++++++++
.../RISCV/MCTargetDesc/RISCVBaseInfo.cpp | 87 ------------------
.../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h | 73 +--------------
llvm/lib/Target/RISCV/RISCVISelLowering.h | 1 -
llvm/lib/TargetParser/RISCVTargetParser.cpp | 91 +++++++++++++++++++
llvm/unittests/Target/RISCV/CMakeLists.txt | 1 -
llvm/unittests/TargetParser/CMakeLists.txt | 1 +
.../RISCVTargetParserTest.cpp} | 7 +-
8 files changed, 173 insertions(+), 165 deletions(-)
rename llvm/unittests/{Target/RISCV/RISCVBaseInfoTest.cpp => TargetParser/RISCVTargetParserTest.cpp} (86%)
diff --git a/llvm/include/llvm/TargetParser/RISCVTargetParser.h b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
index e7da677c7d3ead..4a41b130742558 100644
--- a/llvm/include/llvm/TargetParser/RISCVTargetParser.h
+++ b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
@@ -15,6 +15,8 @@
#define LLVM_TARGETPARSER_RISCVTARGETPARSER_H
#include "llvm/ADT/StringRef.h"
+#include "llvm/Support/MathExtras.h"
+#include "llvm/Support/raw_ostream.h"
namespace llvm {
@@ -33,6 +35,81 @@ void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
bool hasFastUnalignedAccess(StringRef CPU);
} // namespace RISCV
+
+namespace RISCVII {
+enum VLMUL : uint8_t {
+ LMUL_1 = 0,
+ LMUL_2,
+ LMUL_4,
+ LMUL_8,
+ LMUL_RESERVED,
+ LMUL_F8,
+ LMUL_F4,
+ LMUL_F2
+};
+
+enum {
+ TAIL_UNDISTURBED_MASK_UNDISTURBED = 0,
+ TAIL_AGNOSTIC = 1,
+ MASK_AGNOSTIC = 2,
+};
+} // namespace RISCVII
+
+namespace RISCVVType {
+// Is this a SEW value that can be encoded into the VTYPE format.
+inline static bool isValidSEW(unsigned SEW) {
+ return isPowerOf2_32(SEW) && SEW >= 8 && SEW <= 1024;
+}
+
+// Is this a LMUL value that can be encoded into the VTYPE format.
+inline static bool isValidLMUL(unsigned LMUL, bool Fractional) {
+ return isPowerOf2_32(LMUL) && LMUL <= 8 && (!Fractional || LMUL != 1);
+}
+
+unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
+ bool MaskAgnostic);
+
+inline static RISCVII::VLMUL getVLMUL(unsigned VType) {
+ unsigned VLMUL = VType & 0x7;
+ return static_cast<RISCVII::VLMUL>(VLMUL);
+}
+
+// Decode VLMUL into 1,2,4,8 and fractional indicator.
+std::pair<unsigned, bool> decodeVLMUL(RISCVII::VLMUL VLMUL);
+
+inline static RISCVII::VLMUL encodeLMUL(unsigned LMUL, bool Fractional) {
+ assert(isValidLMUL(LMUL, Fractional) && "Unsupported LMUL");
+ unsigned LmulLog2 = Log2_32(LMUL);
+ return static_cast<RISCVII::VLMUL>(Fractional ? 8 - LmulLog2 : LmulLog2);
+}
+
+inline static unsigned decodeVSEW(unsigned VSEW) {
+ assert(VSEW < 8 && "Unexpected VSEW value");
+ return 1 << (VSEW + 3);
+}
+
+inline static unsigned encodeSEW(unsigned SEW) {
+ assert(isValidSEW(SEW) && "Unexpected SEW value");
+ return Log2_32(SEW) - 3;
+}
+
+inline static unsigned getSEW(unsigned VType) {
+ unsigned VSEW = (VType >> 3) & 0x7;
+ return decodeVSEW(VSEW);
+}
+
+inline static bool isTailAgnostic(unsigned VType) { return VType & 0x40; }
+
+inline static bool isMaskAgnostic(unsigned VType) { return VType & 0x80; }
+
+void printVType(unsigned VType, raw_ostream &OS);
+
+unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul);
+
+std::optional<RISCVII::VLMUL>
+getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW);
+} // namespace RISCVVType
+
} // namespace llvm
#endif
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
index be9c7d190b55ac..61f8e71710377e 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
@@ -134,93 +134,6 @@ parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits) {
} // namespace RISCVFeatures
-// Encode VTYPE into the binary format used by the the VSETVLI instruction which
-// is used by our MC layer representation.
-//
-// Bits | Name | Description
-// -----+------------+------------------------------------------------
-// 7 | vma | Vector mask agnostic
-// 6 | vta | Vector tail agnostic
-// 5:3 | vsew[2:0] | Standard element width (SEW) setting
-// 2:0 | vlmul[2:0] | Vector register group multiplier (LMUL) setting
-unsigned RISCVVType::encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW,
- bool TailAgnostic, bool MaskAgnostic) {
- assert(isValidSEW(SEW) && "Invalid SEW");
- unsigned VLMULBits = static_cast<unsigned>(VLMUL);
- unsigned VSEWBits = encodeSEW(SEW);
- unsigned VTypeI = (VSEWBits << 3) | (VLMULBits & 0x7);
- if (TailAgnostic)
- VTypeI |= 0x40;
- if (MaskAgnostic)
- VTypeI |= 0x80;
-
- return VTypeI;
-}
-
-std::pair<unsigned, bool> RISCVVType::decodeVLMUL(RISCVII::VLMUL VLMUL) {
- switch (VLMUL) {
- default:
- llvm_unreachable("Unexpected LMUL value!");
- case RISCVII::VLMUL::LMUL_1:
- case RISCVII::VLMUL::LMUL_2:
- case RISCVII::VLMUL::LMUL_4:
- case RISCVII::VLMUL::LMUL_8:
- return std::make_pair(1 << static_cast<unsigned>(VLMUL), false);
- case RISCVII::VLMUL::LMUL_F2:
- case RISCVII::VLMUL::LMUL_F4:
- case RISCVII::VLMUL::LMUL_F8:
- return std::make_pair(1 << (8 - static_cast<unsigned>(VLMUL)), true);
- }
-}
-
-void RISCVVType::printVType(unsigned VType, raw_ostream &OS) {
- unsigned Sew = getSEW(VType);
- OS << "e" << Sew;
-
- unsigned LMul;
- bool Fractional;
- std::tie(LMul, Fractional) = decodeVLMUL(getVLMUL(VType));
-
- if (Fractional)
- OS << ", mf";
- else
- OS << ", m";
- OS << LMul;
-
- if (isTailAgnostic(VType))
- OS << ", ta";
- else
- OS << ", tu";
-
- if (isMaskAgnostic(VType))
- OS << ", ma";
- else
- OS << ", mu";
-}
-
-unsigned RISCVVType::getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul) {
- unsigned LMul;
- bool Fractional;
- std::tie(LMul, Fractional) = decodeVLMUL(VLMul);
-
- // Convert LMul to a fixed point value with 3 fractional bits.
- LMul = Fractional ? (8 / LMul) : (LMul * 8);
-
- assert(SEW >= 8 && "Unexpected SEW value");
- return (SEW * 8) / LMul;
-}
-
-std::optional<RISCVII::VLMUL>
-RISCVVType::getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW) {
- unsigned Ratio = RISCVVType::getSEWLMULRatio(SEW, VLMUL);
- unsigned EMULFixedPoint = (EEW * 8) / Ratio;
- bool Fractional = EMULFixedPoint < 8;
- unsigned EMUL = Fractional ? 8 / EMULFixedPoint : EMULFixedPoint / 8;
- if (!isValidLMUL(EMUL, Fractional))
- return std::nullopt;
- return RISCVVType::encodeLMUL(EMUL, Fractional);
-}
-
// Include the auto-generated portion of the compress emitter.
#define GEN_UNCOMPRESS_INSTR
#define GEN_COMPRESS_INSTR
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index d7f7859ce4399b..6d0381c30d3e86 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -20,6 +20,7 @@
#include "llvm/ADT/StringSwitch.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/Support/RISCVISAInfo.h"
+#include "llvm/TargetParser/RISCVTargetParser.h"
#include "llvm/TargetParser/SubtargetFeature.h"
namespace llvm {
@@ -124,23 +125,6 @@ enum {
TargetOverlapConstraintTypeMask = 3ULL << TargetOverlapConstraintTypeShift,
};
-enum VLMUL : uint8_t {
- LMUL_1 = 0,
- LMUL_2,
- LMUL_4,
- LMUL_8,
- LMUL_RESERVED,
- LMUL_F8,
- LMUL_F4,
- LMUL_F2
-};
-
-enum {
- TAIL_UNDISTURBED_MASK_UNDISTURBED = 0,
- TAIL_AGNOSTIC = 1,
- MASK_AGNOSTIC = 2,
-};
-
// Helper functions to read TSFlags.
/// \returns the format of the instruction.
static inline unsigned getFormat(uint64_t TSFlags) {
@@ -484,61 +468,6 @@ parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits);
} // namespace RISCVFeatures
-namespace RISCVVType {
-// Is this a SEW value that can be encoded into the VTYPE format.
-inline static bool isValidSEW(unsigned SEW) {
- return isPowerOf2_32(SEW) && SEW >= 8 && SEW <= 1024;
-}
-
-// Is this a LMUL value that can be encoded into the VTYPE format.
-inline static bool isValidLMUL(unsigned LMUL, bool Fractional) {
- return isPowerOf2_32(LMUL) && LMUL <= 8 && (!Fractional || LMUL != 1);
-}
-
-unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
- bool MaskAgnostic);
-
-inline static RISCVII::VLMUL getVLMUL(unsigned VType) {
- unsigned VLMUL = VType & 0x7;
- return static_cast<RISCVII::VLMUL>(VLMUL);
-}
-
-// Decode VLMUL into 1,2,4,8 and fractional indicator.
-std::pair<unsigned, bool> decodeVLMUL(RISCVII::VLMUL VLMUL);
-
-inline static RISCVII::VLMUL encodeLMUL(unsigned LMUL, bool Fractional) {
- assert(isValidLMUL(LMUL, Fractional) && "Unsupported LMUL");
- unsigned LmulLog2 = Log2_32(LMUL);
- return static_cast<RISCVII::VLMUL>(Fractional ? 8 - LmulLog2 : LmulLog2);
-}
-
-inline static unsigned decodeVSEW(unsigned VSEW) {
- assert(VSEW < 8 && "Unexpected VSEW value");
- return 1 << (VSEW + 3);
-}
-
-inline static unsigned encodeSEW(unsigned SEW) {
- assert(isValidSEW(SEW) && "Unexpected SEW value");
- return Log2_32(SEW) - 3;
-}
-
-inline static unsigned getSEW(unsigned VType) {
- unsigned VSEW = (VType >> 3) & 0x7;
- return decodeVSEW(VSEW);
-}
-
-inline static bool isTailAgnostic(unsigned VType) { return VType & 0x40; }
-
-inline static bool isMaskAgnostic(unsigned VType) { return VType & 0x80; }
-
-void printVType(unsigned VType, raw_ostream &OS);
-
-unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul);
-
-std::optional<RISCVII::VLMUL>
-getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW);
-} // namespace RISCVVType
-
namespace RISCVRVC {
bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index a38463f810270a..f90cb4df604761 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -18,7 +18,6 @@
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/TargetLowering.h"
-#include "llvm/TargetParser/RISCVTargetParser.h"
#include <optional>
namespace llvm {
diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp b/llvm/lib/TargetParser/RISCVTargetParser.cpp
index 85cdd1289a9538..7256c1b300f69e 100644
--- a/llvm/lib/TargetParser/RISCVTargetParser.cpp
+++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp
@@ -96,4 +96,95 @@ void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64) {
}
} // namespace RISCV
+
+namespace RISCVVType {
+// Encode VTYPE into the binary format used by the the VSETVLI instruction which
+// is used by our MC layer representation.
+//
+// Bits | Name | Description
+// -----+------------+------------------------------------------------
+// 7 | vma | Vector mask agnostic
+// 6 | vta | Vector tail agnostic
+// 5:3 | vsew[2:0] | Standard element width (SEW) setting
+// 2:0 | vlmul[2:0] | Vector register group multiplier (LMUL) setting
+unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
+ bool MaskAgnostic) {
+ assert(isValidSEW(SEW) && "Invalid SEW");
+ unsigned VLMULBits = static_cast<unsigned>(VLMUL);
+ unsigned VSEWBits = encodeSEW(SEW);
+ unsigned VTypeI = (VSEWBits << 3) | (VLMULBits & 0x7);
+ if (TailAgnostic)
+ VTypeI |= 0x40;
+ if (MaskAgnostic)
+ VTypeI |= 0x80;
+
+ return VTypeI;
+}
+
+std::pair<unsigned, bool> decodeVLMUL(RISCVII::VLMUL VLMUL) {
+ switch (VLMUL) {
+ default:
+ llvm_unreachable("Unexpected LMUL value!");
+ case RISCVII::VLMUL::LMUL_1:
+ case RISCVII::VLMUL::LMUL_2:
+ case RISCVII::VLMUL::LMUL_4:
+ case RISCVII::VLMUL::LMUL_8:
+ return std::make_pair(1 << static_cast<unsigned>(VLMUL), false);
+ case RISCVII::VLMUL::LMUL_F2:
+ case RISCVII::VLMUL::LMUL_F4:
+ case RISCVII::VLMUL::LMUL_F8:
+ return std::make_pair(1 << (8 - static_cast<unsigned>(VLMUL)), true);
+ }
+}
+
+void printVType(unsigned VType, raw_ostream &OS) {
+ unsigned Sew = getSEW(VType);
+ OS << "e" << Sew;
+
+ unsigned LMul;
+ bool Fractional;
+ std::tie(LMul, Fractional) = decodeVLMUL(getVLMUL(VType));
+
+ if (Fractional)
+ OS << ", mf";
+ else
+ OS << ", m";
+ OS << LMul;
+
+ if (isTailAgnostic(VType))
+ OS << ", ta";
+ else
+ OS << ", tu";
+
+ if (isMaskAgnostic(VType))
+ OS << ", ma";
+ else
+ OS << ", mu";
+}
+
+unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul) {
+ unsigned LMul;
+ bool Fractional;
+ std::tie(LMul, Fractional) = decodeVLMUL(VLMul);
+
+ // Convert LMul to a fixed point value with 3 fractional bits.
+ LMul = Fractional ? (8 / LMul) : (LMul * 8);
+
+ assert(SEW >= 8 && "Unexpected SEW value");
+ return (SEW * 8) / LMul;
+}
+
+std::optional<RISCVII::VLMUL>
+getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW) {
+ unsigned Ratio = RISCVVType::getSEWLMULRatio(SEW, VLMUL);
+ unsigned EMULFixedPoint = (EEW * 8) / Ratio;
+ bool Fractional = EMULFixedPoint < 8;
+ unsigned EMUL = Fractional ? 8 / EMULFixedPoint : EMULFixedPoint / 8;
+ if (!isValidLMUL(EMUL, Fractional))
+ return std::nullopt;
+ return RISCVVType::encodeLMUL(EMUL, Fractional);
+}
+
+} // namespace RISCVVType
+
} // namespace llvm
diff --git a/llvm/unittests/Target/RISCV/CMakeLists.txt b/llvm/unittests/Target/RISCV/CMakeLists.txt
index d80d29b7f0dada..b58d605355bad8 100644
--- a/llvm/unittests/Target/RISCV/CMakeLists.txt
+++ b/llvm/unittests/Target/RISCV/CMakeLists.txt
@@ -16,7 +16,6 @@ set(LLVM_LINK_COMPONENTS
add_llvm_target_unittest(RISCVTests
MCInstrAnalysisTest.cpp
- RISCVBaseInfoTest.cpp
RISCVInstrInfoTest.cpp
)
diff --git a/llvm/unittests/TargetParser/CMakeLists.txt b/llvm/unittests/TargetParser/CMakeLists.txt
index 501acc04468702..7df98d83d77a30 100644
--- a/llvm/unittests/TargetParser/CMakeLists.txt
+++ b/llvm/unittests/TargetParser/CMakeLists.txt
@@ -8,6 +8,7 @@ add_llvm_unittest(TargetParserTests
Host.cpp
TargetParserTest.cpp
TripleTest.cpp
+ RISCVTargetParserTest.cpp
)
target_link_libraries(TargetParserTests PRIVATE LLVMTestingSupport)
diff --git a/llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp b/llvm/unittests/TargetParser/RISCVTargetParserTest.cpp
similarity index 86%
rename from llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp
rename to llvm/unittests/TargetParser/RISCVTargetParserTest.cpp
index 0e4c90caaaefd7..68338b569a2082 100644
--- a/llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVTargetParserTest.cpp
@@ -1,4 +1,4 @@
-//===- RISCVBaseInfoTest.cpp - RISCVBaseInfo unit tests ----------===//
+//===---- RISCVTargetParserTest.cpp - RISCVTargetParser unit tests --------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
@@ -6,14 +6,13 @@
//
//===----------------------------------------------------------------------===//
-#include "MCTargetDesc/RISCVBaseInfo.h"
-
+#include "llvm/TargetParser/RISCVTargetParser.h"
#include "gtest/gtest.h"
using namespace llvm;
namespace {
-TEST(RISCVBaseInfo, CheckSameRatioLMUL) {
+TEST(RISCVVType, CheckSameRatioLMUL) {
// Smaller LMUL.
EXPECT_EQ(RISCVII::LMUL_1,
RISCVVType::getSameRatioLMUL(16, RISCVII::LMUL_2, 8));
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