[llvm] [GlobalISel] Handle div-by-pow2 (PR #83155)
Shilei Tian via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 27 09:07:50 PST 2024
https://github.com/shiltian created https://github.com/llvm/llvm-project/pull/83155
This patch adds similar handling of div-by-pow2 as in `SelectionDAG`.
>From f4139992fc3dd30d70850e4611c8a751c194cf50 Mon Sep 17 00:00:00 2001
From: Shilei Tian <i at tianshilei.me>
Date: Tue, 27 Feb 2024 12:02:27 -0500
Subject: [PATCH] [GlobalISel] Handle div-by-pow2
This patch adds similar handling of div-by-pow2 as in `SelectionDAG`.
---
.../llvm/CodeGen/GlobalISel/CombinerHelper.h | 3 +
.../include/llvm/Target/GlobalISel/Combine.td | 14 +++--
.../lib/CodeGen/GlobalISel/CombinerHelper.cpp | 58 ++++++++++++++++++-
llvm/test/CodeGen/AMDGPU/div_i128.ll | 4 +-
4 files changed, 72 insertions(+), 7 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
index 23728636498ba0..8e3c9fc4dfcd2b 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
@@ -673,6 +673,9 @@ class CombinerHelper {
bool matchSDivByConst(MachineInstr &MI);
void applySDivByConst(MachineInstr &MI);
+ bool matchSDivByPow2(MachineInstr &MI);
+ void applySDivByPow2(MachineInstr &MI);
+
// G_UMULH x, (1 << c)) -> x >> (bitwidth - c)
bool matchUMulHToLShr(MachineInstr &MI);
void applyUMulHToLShr(MachineInstr &MI);
diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td
index 17757ca3e41111..dd665666cb8e03 100644
--- a/llvm/include/llvm/Target/GlobalISel/Combine.td
+++ b/llvm/include/llvm/Target/GlobalISel/Combine.td
@@ -264,7 +264,7 @@ def combine_extracted_vector_load : GICombineRule<
(match (wip_match_opcode G_EXTRACT_VECTOR_ELT):$root,
[{ return Helper.matchCombineExtractedVectorLoad(*${root}, ${matchinfo}); }]),
(apply [{ Helper.applyBuildFn(*${root}, ${matchinfo}); }])>;
-
+
def combine_indexed_load_store : GICombineRule<
(defs root:$root, indexed_load_store_matchdata:$matchinfo),
(match (wip_match_opcode G_LOAD, G_SEXTLOAD, G_ZEXTLOAD, G_STORE):$root,
@@ -1005,7 +1005,13 @@ def sdiv_by_const : GICombineRule<
[{ return Helper.matchSDivByConst(*${root}); }]),
(apply [{ Helper.applySDivByConst(*${root}); }])>;
-def intdiv_combines : GICombineGroup<[udiv_by_const, sdiv_by_const]>;
+def sdiv_by_pow2 : GICombineRule<
+ (defs root:$root),
+ (match (wip_match_opcode G_SDIV):$root,
+ [{ return Helper.matchSDivByPow2(*${root}); }]),
+ (apply [{ Helper.applySDivByPow2(*${root}); }])>;
+
+def intdiv_combines : GICombineGroup<[udiv_by_const, sdiv_by_const, sdiv_by_pow2]>;
def reassoc_ptradd : GICombineRule<
(defs root:$root, build_fn_matchinfo:$matchinfo),
@@ -1325,7 +1331,7 @@ def constant_fold_binops : GICombineGroup<[constant_fold_binop,
def all_combines : GICombineGroup<[trivial_combines, insert_vec_elt_combines,
extract_vec_elt_combines, combines_for_extload, combine_extracted_vector_load,
- undef_combines, identity_combines, phi_combines,
+ undef_combines, identity_combines, phi_combines,
simplify_add_to_sub, hoist_logic_op_with_same_opcode_hands, shifts_too_big,
reassocs, ptr_add_immed_chain,
shl_ashr_to_sext_inreg, sext_inreg_of_load,
@@ -1342,7 +1348,7 @@ def all_combines : GICombineGroup<[trivial_combines, insert_vec_elt_combines,
intdiv_combines, mulh_combines, redundant_neg_operands,
and_or_disjoint_mask, fma_combines, fold_binop_into_select,
sub_add_reg, select_to_minmax, redundant_binop_in_equality,
- fsub_to_fneg, commute_constant_to_rhs, match_ands, match_ors,
+ fsub_to_fneg, commute_constant_to_rhs, match_ands, match_ors,
combine_concat_vector]>;
// A combine group used to for prelegalizer combiners at -O0. The combines in
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index 2f18a64ca285bd..05c493261171fc 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -1490,7 +1490,7 @@ void CombinerHelper::applyOptBrCondByInvertingCond(MachineInstr &MI,
Observer.changedInstr(*BrCond);
}
-
+
bool CombinerHelper::tryEmitMemcpyInline(MachineInstr &MI) {
MachineIRBuilder HelperBuilder(MI);
GISelObserverWrapper DummyObserver;
@@ -5286,6 +5286,62 @@ MachineInstr *CombinerHelper::buildSDivUsingMul(MachineInstr &MI) {
return MIB.buildMul(Ty, Res, Factor);
}
+bool CombinerHelper::matchSDivByPow2(MachineInstr &MI) {
+ assert(MI.getOpcode() == TargetOpcode::G_SDIV && "Expected SDIV");
+ auto &SDiv = cast<GenericMachineInstr>(MI);
+ Register RHS = SDiv.getReg(2);
+ auto MatchPow2 = [&](const Constant *C) {
+ if (auto *CI = dyn_cast<ConstantInt>(C))
+ return CI->getValue().isPowerOf2() || CI->getValue().isNegatedPowerOf2();
+ return false;
+ };
+ return matchUnaryPredicate(MRI, RHS, MatchPow2, /* AllowUndefs */ false);
+}
+
+void CombinerHelper::applySDivByPow2(MachineInstr &MI) {
+ assert(MI.getOpcode() == TargetOpcode::G_SDIV && "Expected SDIV");
+ auto &SDiv = cast<GenericMachineInstr>(MI);
+ Register Dst = SDiv.getReg(0);
+ Register LHS = SDiv.getReg(1);
+ Register RHS = SDiv.getReg(2);
+ LLT Ty = MRI.getType(Dst);
+ LLT ShiftAmtTy = getTargetLowering().getPreferredShiftAmountTy(Ty);
+ LLT CVT = LLT::scalar(1);
+
+ Builder.setInstrAndDebugLoc(MI);
+
+ unsigned Bitwidth = Ty.getScalarSizeInBits();
+ auto Bits = Builder.buildConstant(ShiftAmtTy, Bitwidth);
+ auto C1 = Builder.buildCTTZ(Ty, RHS);
+ C1 = Builder.buildZExtOrTrunc(ShiftAmtTy, C1);
+ auto Inexact = Builder.buildSub(ShiftAmtTy, Bits, C1);
+ // TODO: Need to check whether Inexact is constant
+ auto Sign = Builder.buildAShr(
+ Ty, LHS, Builder.buildConstant(ShiftAmtTy, Bitwidth - 1));
+ // Add (LHS < 0) ? abs2 - 1 : 0;
+ auto Srl = Builder.buildShl(Ty, Sign, Inexact);
+ auto Add = Builder.buildAdd(Ty, LHS, Srl);
+ auto Sra = Builder.buildAShr(Ty, Add, C1);
+ // Special case: (sdiv X, 1) -> X
+ // Special Case: (sdiv X, -1) -> 0-X
+ auto One = Builder.buildConstant(Ty, 1);
+ auto AllOnes = Builder.buildConstant(Ty, APInt::getAllOnes(Bitwidth));
+ auto IsOne = Builder.buildICmp(CmpInst::Predicate::ICMP_EQ, CVT, RHS, One);
+ auto IsAllOnes =
+ Builder.buildICmp(CmpInst::Predicate::ICMP_EQ, CVT, RHS, AllOnes);
+ auto IsOneOrAllOnes = Builder.buildOr(CVT, IsOne, IsAllOnes);
+ Sra = Builder.buildSelect(Ty, IsOneOrAllOnes, LHS, Sra);
+
+ // If dividing by a positive value, we're done. Otherwise, the result must
+ // be negated.
+ auto Zero = Builder.buildConstant(Ty, 0);
+ auto Sub = Builder.buildSub(Ty, Zero, Sra);
+ auto IsNeg = Builder.buildICmp(CmpInst::Predicate::ICMP_SLT, CVT, RHS, Zero);
+ auto Res = Builder.buildSelect(Ty, IsNeg, Sub, Sra);
+
+ replaceSingleDefInstWithReg(MI, Res->getOperand(0).getReg());
+}
+
bool CombinerHelper::matchUMulHToLShr(MachineInstr &MI) {
assert(MI.getOpcode() == TargetOpcode::G_UMULH);
Register RHS = MI.getOperand(2).getReg();
diff --git a/llvm/test/CodeGen/AMDGPU/div_i128.ll b/llvm/test/CodeGen/AMDGPU/div_i128.ll
index 5296ad3ab51d31..0abbef2df38ccd 100644
--- a/llvm/test/CodeGen/AMDGPU/div_i128.ll
+++ b/llvm/test/CodeGen/AMDGPU/div_i128.ll
@@ -3,8 +3,8 @@
; RUN: llc -O0 -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o - %s | FileCheck -check-prefixes=GFX9-O0,GFX9-SDAG-O0 %s
; FIXME: GlobalISel missing the power-of-2 cases in legalization. https://github.com/llvm/llvm-project/issues/80671
-; xUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o - %s | FileCheck -check-prefixes=GFX9,GFX9 %s
-; xUN: llc -O0 -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o - %s | FileCheck -check-prefixes=GFX9-O0,GFX9-O0 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o - %s | FileCheck -check-prefixes=GFX9,GFX9 %s
+; RUN: llc -O0 -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o - %s | FileCheck -check-prefixes=GFX9-O0,GFX9-O0 %s
define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-LABEL: v_sdiv_i128_vv:
More information about the llvm-commits
mailing list