[llvm] [RISCV] Recursively split concat_vector into smaller LMULs (PR #83035)

[Luke Lau via llvm-commits]

================
@@ -7,14 +7,14 @@
 define <4 x i1> @load_large_vector(ptr %p) {
 ; ZVE32X-LABEL: load_large_vector:
 ; ZVE32X:       # %bb.0:
-; ZVE32X-NEXT:    ld a1, 80(a0)
-; ZVE32X-NEXT:    ld a2, 72(a0)
-; ZVE32X-NEXT:    ld a3, 56(a0)
-; ZVE32X-NEXT:    ld a4, 32(a0)
-; ZVE32X-NEXT:    ld a5, 24(a0)
-; ZVE32X-NEXT:    ld a6, 48(a0)
-; ZVE32X-NEXT:    ld a7, 8(a0)
-; ZVE32X-NEXT:    ld a0, 0(a0)
+; ZVE32X-NEXT:    ld a1, 8(a0)
----------------
lukel97 wrote:

I'm not sure why this combine is specifically triggering these loads to be come unordered, but https://github.com/llvm/llvm-project/pull/73789 may fix this

https://github.com/llvm/llvm-project/pull/83035