[llvm] ebb64d8 - [GlobalISel] Make the Combiner insert G_FREEZE when converting G_SELECT to binary operations. (#82733)
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Mon Feb 26 07:50:42 PST 2024
Author: Owen Anderson
Date: 2024-02-26T10:50:37-05:00
New Revision: ebb64d8370f9f425f10c4b084aa62adc2926e2dd
URL: https://github.com/llvm/llvm-project/commit/ebb64d8370f9f425f10c4b084aa62adc2926e2dd
DIFF: https://github.com/llvm/llvm-project/commit/ebb64d8370f9f425f10c4b084aa62adc2926e2dd.diff
LOG: [GlobalISel] Make the Combiner insert G_FREEZE when converting G_SELECT to binary operations. (#82733)
This is needed because the binary operators (G_OR and G_AND) do
not have the poison-suppressing semantics of G_SELECT.
Fixes https://github.com/llvm/llvm-project/issues/72475
Added:
Modified:
llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
llvm/test/CodeGen/AArch64/GlobalISel/combine-select.mir
llvm/test/CodeGen/AArch64/cmp-chains.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index e8a5c6fedc395a..2f18a64ca285bd 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -6511,7 +6511,8 @@ bool CombinerHelper::tryFoldBoolSelectToLogic(GSelect *Select,
B.setInstrAndDebugLoc(*Select);
Register Ext = MRI.createGenericVirtualRegister(TrueTy);
B.buildZExtOrTrunc(Ext, Cond);
- B.buildOr(DstReg, Ext, False, Flags);
+ auto FreezeFalse = B.buildFreeze(TrueTy, False);
+ B.buildOr(DstReg, Ext, FreezeFalse, Flags);
};
return true;
}
@@ -6523,7 +6524,8 @@ bool CombinerHelper::tryFoldBoolSelectToLogic(GSelect *Select,
B.setInstrAndDebugLoc(*Select);
Register Ext = MRI.createGenericVirtualRegister(TrueTy);
B.buildZExtOrTrunc(Ext, Cond);
- B.buildAnd(DstReg, Ext, True);
+ auto FreezeTrue = B.buildFreeze(TrueTy, True);
+ B.buildAnd(DstReg, Ext, FreezeTrue);
};
return true;
}
@@ -6538,7 +6540,8 @@ bool CombinerHelper::tryFoldBoolSelectToLogic(GSelect *Select,
// Then an ext to match the destination register.
Register Ext = MRI.createGenericVirtualRegister(TrueTy);
B.buildZExtOrTrunc(Ext, Inner);
- B.buildOr(DstReg, Ext, True, Flags);
+ auto FreezeTrue = B.buildFreeze(TrueTy, True);
+ B.buildOr(DstReg, Ext, FreezeTrue, Flags);
};
return true;
}
@@ -6553,7 +6556,8 @@ bool CombinerHelper::tryFoldBoolSelectToLogic(GSelect *Select,
// Then an ext to match the destination register.
Register Ext = MRI.createGenericVirtualRegister(TrueTy);
B.buildZExtOrTrunc(Ext, Inner);
- B.buildAnd(DstReg, Ext, False);
+ auto FreezeFalse = B.buildFreeze(TrueTy, False);
+ B.buildAnd(DstReg, Ext, FreezeFalse);
};
return true;
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-select.mir
index da35d60981ad38..7b73c8cec47746 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-select.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-select.mir
@@ -118,7 +118,8 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: %c:_(s1) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: %f:_(s1) = G_TRUNC [[COPY1]](s64)
- ; CHECK-NEXT: %sel:_(s1) = G_OR %c, %f
+ ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s1) = G_FREEZE %f
+ ; CHECK-NEXT: %sel:_(s1) = G_OR %c, [[FREEZE]]
; CHECK-NEXT: %ext:_(s32) = G_ANYEXT %sel(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
%0:_(s64) = COPY $x0
@@ -144,7 +145,8 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: %c:_(s1) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: %f:_(s1) = G_TRUNC [[COPY1]](s64)
- ; CHECK-NEXT: %sel:_(s1) = G_OR %c, %f
+ ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s1) = G_FREEZE %f
+ ; CHECK-NEXT: %sel:_(s1) = G_OR %c, [[FREEZE]]
; CHECK-NEXT: %ext:_(s32) = G_ANYEXT %sel(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
%0:_(s64) = COPY $x0
@@ -171,7 +173,8 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d2
; CHECK-NEXT: %c:_(<2 x s1>) = G_TRUNC [[COPY]](<2 x s32>)
; CHECK-NEXT: %f:_(<2 x s1>) = G_TRUNC [[COPY1]](<2 x s32>)
- ; CHECK-NEXT: %sel:_(<2 x s1>) = G_OR %c, %f
+ ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<2 x s1>) = G_FREEZE %f
+ ; CHECK-NEXT: %sel:_(<2 x s1>) = G_OR %c, [[FREEZE]]
; CHECK-NEXT: %ext:_(<2 x s32>) = G_ANYEXT %sel(<2 x s1>)
; CHECK-NEXT: $d0 = COPY %ext(<2 x s32>)
%0:_(<2 x s32>) = COPY $d0
@@ -199,7 +202,8 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK-NEXT: %c:_(s1) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: %t:_(s1) = G_TRUNC [[COPY1]](s64)
- ; CHECK-NEXT: %sel:_(s1) = G_AND %c, %t
+ ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s1) = G_FREEZE %t
+ ; CHECK-NEXT: %sel:_(s1) = G_AND %c, [[FREEZE]]
; CHECK-NEXT: %ext:_(s32) = G_ANYEXT %sel(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
%0:_(s64) = COPY $x0
@@ -226,7 +230,8 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK-NEXT: %c:_(s1) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: %t:_(s1) = G_TRUNC [[COPY1]](s64)
- ; CHECK-NEXT: %sel:_(s1) = G_AND %c, %t
+ ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s1) = G_FREEZE %t
+ ; CHECK-NEXT: %sel:_(s1) = G_AND %c, [[FREEZE]]
; CHECK-NEXT: %ext:_(s32) = G_ANYEXT %sel(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
%0:_(s64) = COPY $x0
@@ -255,7 +260,8 @@ body: |
; CHECK-NEXT: %t:_(s1) = G_TRUNC [[COPY1]](s64)
; CHECK-NEXT: %one:_(s1) = G_CONSTANT i1 true
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR %c, %one
- ; CHECK-NEXT: %sel:_(s1) = G_OR [[XOR]], %t
+ ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s1) = G_FREEZE %t
+ ; CHECK-NEXT: %sel:_(s1) = G_OR [[XOR]], [[FREEZE]]
; CHECK-NEXT: %ext:_(s32) = G_ANYEXT %sel(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
%0:_(s64) = COPY $x0
@@ -284,7 +290,8 @@ body: |
; CHECK-NEXT: %f:_(s1) = G_TRUNC [[COPY1]](s64)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR %c, [[C]]
- ; CHECK-NEXT: %sel:_(s1) = G_AND [[XOR]], %f
+ ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s1) = G_FREEZE %f
+ ; CHECK-NEXT: %sel:_(s1) = G_AND [[XOR]], [[FREEZE]]
; CHECK-NEXT: %ext:_(s32) = G_ANYEXT %sel(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
%0:_(s64) = COPY $x0
diff --git a/llvm/test/CodeGen/AArch64/cmp-chains.ll b/llvm/test/CodeGen/AArch64/cmp-chains.ll
index c4ad84d9fa25ba..1d9f39e5185939 100644
--- a/llvm/test/CodeGen/AArch64/cmp-chains.ll
+++ b/llvm/test/CodeGen/AArch64/cmp-chains.ll
@@ -109,7 +109,8 @@ define i32 @cmp_or2(i32 %0, i32 %1, i32 %2, i32 %3) {
; GISEL-NEXT: cset w8, lo
; GISEL-NEXT: cmp w2, w3
; GISEL-NEXT: cset w9, ne
-; GISEL-NEXT: orr w0, w8, w9
+; GISEL-NEXT: orr w8, w8, w9
+; GISEL-NEXT: and w0, w8, #0x1
; GISEL-NEXT: ret
%5 = icmp ult i32 %0, %1
%6 = icmp ne i32 %2, %3
@@ -137,7 +138,8 @@ define i32 @cmp_or3(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5) {
; GISEL-NEXT: cmp w4, w5
; GISEL-NEXT: orr w8, w8, w9
; GISEL-NEXT: cset w9, ne
-; GISEL-NEXT: orr w0, w8, w9
+; GISEL-NEXT: orr w8, w8, w9
+; GISEL-NEXT: and w0, w8, #0x1
; GISEL-NEXT: ret
%7 = icmp ult i32 %0, %1
%8 = icmp ugt i32 %2, %3
@@ -171,7 +173,8 @@ define i32 @cmp_or4(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32
; GISEL-NEXT: orr w8, w8, w9
; GISEL-NEXT: cset w11, eq
; GISEL-NEXT: orr w9, w10, w11
-; GISEL-NEXT: orr w0, w8, w9
+; GISEL-NEXT: orr w8, w8, w9
+; GISEL-NEXT: and w0, w8, #0x1
; GISEL-NEXT: ret
%9 = icmp ult i32 %0, %1
%10 = icmp ugt i32 %2, %3
@@ -199,7 +202,8 @@ define i32 @true_or2(i32 %0, i32 %1) {
; GISEL-NEXT: cset w8, ne
; GISEL-NEXT: cmp w1, #0
; GISEL-NEXT: cset w9, ne
-; GISEL-NEXT: orr w0, w8, w9
+; GISEL-NEXT: orr w8, w8, w9
+; GISEL-NEXT: and w0, w8, #0x1
; GISEL-NEXT: ret
%3 = icmp ne i32 %0, 0
%4 = icmp ne i32 %1, 0
@@ -227,7 +231,8 @@ define i32 @true_or3(i32 %0, i32 %1, i32 %2) {
; GISEL-NEXT: cmp w2, #0
; GISEL-NEXT: orr w8, w8, w9
; GISEL-NEXT: cset w9, ne
-; GISEL-NEXT: orr w0, w8, w9
+; GISEL-NEXT: orr w8, w8, w9
+; GISEL-NEXT: and w0, w8, #0x1
; GISEL-NEXT: ret
%4 = icmp ne i32 %0, 0
%5 = icmp ne i32 %1, 0
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