[llvm] [AMDGPU][AsmParser] Allow `v_writelane_b32` to use SGPR and M0 as source operands at the same time (PR #78827)

[Joe Nash via llvm-commits]

https://github.com/Sisyph commented:

AMDGPUInstructionSelector::selectWritelane suggests that on targets where we can support 2 SGPRs per instruction (gfx10+) this is not a special case. That means' this is is only a behavior change for V_WRITELANE_B32_gfx6_gfx7 and V_WRITELANE_B32_vi. Can you please confirm that, and remove the newer versions of the instruction from your special case?

https://github.com/llvm/llvm-project/pull/78827