[llvm] [AMDGPU][AsmParser] Allow `v_writelane_b32` to use SGPR and M0 as source operands at the same time (PR #78827)

[Joe Nash via llvm-commits]

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@@ -3524,6 +3524,34 @@ bool AMDGPUAsmParser::validateConstantBusLimitations(
       !isVOPD(Opcode))
     return true;
 
+  // Based on the comment for `AMDGPUInstructionSelector::selectWritelane`:
+  // Writelane is special in that it can use SGPR and M0 (which would normally
+  // count as using the constant bus twice - but in this case it is allowed
+  // since the lane selector doesn't count as a use of the constant bus).
+  // However, it is still required to abide by the 1 SGPR rule.
+  switch (Opcode) {
+  default:
+    break;
+  case V_WRITELANE_B32_e64_gfx11:
----------------
Sisyph wrote:

This is basically the best way. SIInstrFlags bits can be used, but they are a limited resource. You could also create a tablegen mapping table such as is used for isVOPD, but it is probably overkill for this. 

https://github.com/llvm/llvm-project/pull/78827