[llvm] [RISCV][GISEL] Add vector RegisterBanks and vector support in getRegBankFromRegClass (PR #71541)

[Craig Topper via llvm-commits]

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@@ -14,3 +14,15 @@ def GPRRegBank : RegisterBank<"GPRB", [GPR]>;
 
 /// Floating Point Registers: F.
 def FPRRegBank : RegisterBank<"FPRB", [FPR64]>;
+
+/// Vector Register Banks:
+def VRRegBank : RegisterBank<"VRB", [VR]>;
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topperc wrote:

> Are you sure this is the case? The docs say `Register Banks are a means to constrain the register allocator...`.

Once we do instruction selection every register operand or a selected instruction is a virtual register with a register class assigned to it. The register bank and LLT are gone, or at least not used later.

https://github.com/llvm/llvm-project/pull/71541