[llvm] [RISCV][GISEL] Add vector RegisterBanks and vector support in getRegBankFromRegClass (PR #71541)

[Craig Topper via llvm-commits]

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@@ -14,3 +14,15 @@ def GPRRegBank : RegisterBank<"GPRB", [GPR]>;
 
 /// Floating Point Registers: F.
 def FPRRegBank : RegisterBank<"FPRB", [FPR64]>;
+
+/// Vector Register Banks:
+def VRRegBank : RegisterBank<"VRB", [VR]>;
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topperc wrote:

> It looks like its going from RegClass + LLT -> RegBank. I guess I am confused what the register banks are useful for?

It should be RegBank+LLT->RegClass like the function name says. It returns 3 values today, `RISCV::GPRRegClass`, `RISCV::FPR32RegClass` or `RISCV::FPR64RegClass`

https://github.com/llvm/llvm-project/pull/71541