[PATCH] D156642: libunwind: riscv: disable vector test when __riscv_v not defined

[Sean Cross via Phabricator via llvm-commits]

xobs added a comment.

The other issue is that without this change, libunwind cannot compile on targets such as rv32imac since that instruction set does not include `csrr` as an opcode.

If you like (and if it's possible to do so), I can update the description to reflect that fact. Or we can gate it on `__riscv_zicsr` instead, as suggested in https://reviews.llvm.org/D136264#4545515


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D156642/new/

https://reviews.llvm.org/D156642