[llvm] 0c7d897 - [RISCV] Rename DecoderNamespace for XCVsimd to be consistent with other XCV extensions. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-07-30T12:00:46-07:00
New Revision: 0c7d897627248896f890e3b8ffd6bab1cc5ed746

URL: https://github.com/llvm/llvm-project/commit/0c7d897627248896f890e3b8ffd6bab1cc5ed746
DIFF: https://github.com/llvm/llvm-project/commit/0c7d897627248896f890e3b8ffd6bab1cc5ed746.diff

LOG: [RISCV] Rename DecoderNamespace for XCVsimd to be consistent with other XCV extensions. NFC

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index c02c4b1b42b30d..9ec69cf6e18751 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -567,7 +567,7 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
                           "CORE-V MAC custom opcode table");
     TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCValu, DecoderTableXCValu32,
                           "CORE-V ALU custom opcode table");
-    TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVsimd, DecoderTableCoreVSIMD32,
+    TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVsimd, DecoderTableXCVsimd32,
                           "CORE-V SIMD extensions custom opcode table");
     TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbi, DecoderTableXCVbi32,
                           "CORE-V Immediate Branching custom opcode table");

diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
index c6b780e2774405..ad461184418588 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
@@ -311,7 +311,7 @@ class CVInstSIMDRR<bits<5> funct5, bit F, bit funct1, bits<3> funct3,
   let Inst{14-12} = funct3;
   let Inst{11-7} = rd;
   let Inst{6-0} = opcode.Value;
-  let DecoderNamespace = "CoreVSIMD";
+  let DecoderNamespace = "XCVsimd";
 }
 
 class CVInstSIMDRI<bits<5> funct5, bit F, bits<3> funct3, RISCVOpcode opcode,
@@ -329,7 +329,7 @@ class CVInstSIMDRI<bits<5> funct5, bit F, bits<3> funct3, RISCVOpcode opcode,
   let Inst{14-12} = funct3;
   let Inst{11-7} = rd;
   let Inst{6-0} = opcode.Value;
-  let DecoderNamespace = "CoreVSIMD";
+  let DecoderNamespace = "XCVsimd";
 }
 
 class CVSIMDRR<bits<5> funct5, bit F, bit funct1, bits<3> funct3,