[PATCH] D156544: Add more efficient vector bitcast for v16i8 on AArch64.

[Lawrence Benson via Phabricator via llvm-commits]

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We previously split the vector into two halves and performed two vector reduce operations followed by bit shifting and bitwise or. Now, we use NEON's zip1 to concatenate
the halves in a smart way and then perform only a single vector reduce. This boosts performance quite a bit for this small routine, as vector reduce is a rather expensive 
intruction. Original discussion for this started in: https://reviews.llvm.org/D145301


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D156544

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
  llvm/test/CodeGen/AArch64/vec-combine-compare-truncate-store.ll

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