[PATCH] D156390: [SDAG][RISCV] Avoid expanding is-power-of-2 pattern on riscv32/64 with zbb

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a subscriber: luke957.
craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:17502
+  if (VT.isVector())
+    return isTypeLegal(VT) && Subtarget.hasStdExtZvbb();
+  return Subtarget.hasStdExtZbb() && (VT == MVT::i32 || VT == MVT::i64);
----------------
dtcxzyw wrote:
> luke wrote:
> > I think if we check that the operation is legal then we don’t need to check for zbb/zvbb, since it’s only legal with those extensions
> I am not familiar with the riscv vector crypto extension. I just do the same check as https://github.com/llvm/llvm-project/blob/3c4d2221de0e9e7b259a308aab7e72e3f2f926f1/llvm/lib/Target/RISCV/RISCVISelLowering.cpp#L764.
> 
> It is worth noting that `isOperationLegal(ISD::CTPOP, MVT::i32)` returns false on rv64gc_zbb. We will miss some optimizations if we only check the legality of `ctpop`.
> 
@luke957 it won't be "legal" for fixed vectors since we will need to Custom lower to a RISCVISD node with VL.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156390/new/

https://reviews.llvm.org/D156390