[PATCH] D156319: [RISCV] Relax ta/ma policy into tu/mu in InsertVSETVLI

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D156319#4535006 <https://reviews.llvm.org/D156319#4535006>, @luke wrote:

> This reduces the number of vsetvli toggles and improves code size at least, but I can't comment on the effect of undisturbed on register renaming etc.

This can create false dependencies on out of order CPUs that will prevent instructions from being executed until the previous writer of their destination register has completed.


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https://reviews.llvm.org/D156319