[llvm] 0def4e6 - Revert "[AArch64] Merge LDRSWpre-LD[U]RSW pair into LDPSWpre"
Alexander Kornienko via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 26 07:22:29 PDT 2023
Author: Alexander Kornienko
Date: 2023-07-26T16:22:24+02:00
New Revision: 0def4e6b0f638b97a73bd4674365961d8fabda28
URL: https://github.com/llvm/llvm-project/commit/0def4e6b0f638b97a73bd4674365961d8fabda28
DIFF: https://github.com/llvm/llvm-project/commit/0def4e6b0f638b97a73bd4674365961d8fabda28.diff
LOG: Revert "[AArch64] Merge LDRSWpre-LD[U]RSW pair into LDPSWpre"
This reverts commit b0093e13fcfdd4eea5bbd7ae57d3d1b82f4135c3 due to a miscompile
under MSan. See https://reviews.llvm.org/D152407#4533478 for more details.
Reviewed By: asmok-g
Differential Revision: https://reviews.llvm.org/D156328
Added:
Modified:
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 9d901fd70446c3..bd03ffaafab108 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -2228,7 +2228,6 @@ bool AArch64InstrInfo::hasUnscaledLdStOffset(unsigned Opc) {
case AArch64::LDRWpre:
case AArch64::LDURXi:
case AArch64::LDRXpre:
- case AArch64::LDRSWpre:
case AArch64::LDURSWi:
case AArch64::LDURHHi:
case AArch64::LDURBBi:
@@ -2438,7 +2437,6 @@ bool AArch64InstrInfo::isPairableLdStInst(const MachineInstr &MI) {
case AArch64::LDURXi:
case AArch64::LDRXpre:
case AArch64::LDURSWi:
- case AArch64::LDRSWpre:
return true;
}
}
@@ -2559,8 +2557,7 @@ bool AArch64InstrInfo::isCandidateToMergeOrPair(const MachineInstr &MI) const {
// Can't merge/pair if the instruction modifies the base register.
// e.g., ldr x0, [x0]
// This case will never occur with an FI base.
- // However, if the instruction is an LDR<S,D,Q,W,X,SW>pre or
- // STR<S,D,Q,W,X>pre, it can be merged.
+ // However, if the instruction is an LDR/STR<S,D,Q,W,X>pre, it can be merged.
// For example:
// ldr q0, [x11, #32]!
// ldr q1, [x11, #16]
@@ -3137,7 +3134,6 @@ int AArch64InstrInfo::getMemScale(unsigned Opc) {
case AArch64::LDRSpre:
case AArch64::LDRSWui:
case AArch64::LDURSWi:
- case AArch64::LDRSWpre:
case AArch64::LDRWpre:
case AArch64::LDRWui:
case AArch64::LDURWi:
@@ -3193,7 +3189,6 @@ bool AArch64InstrInfo::isPreLd(const MachineInstr &MI) {
return false;
case AArch64::LDRWpre:
case AArch64::LDRXpre:
- case AArch64::LDRSWpre:
case AArch64::LDRSpre:
case AArch64::LDRDpre:
case AArch64::LDRQpre:
diff --git a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
index 419b471db3a37c..41af5522d967db 100644
--- a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
@@ -293,8 +293,6 @@ static unsigned getMatchingNonSExtOpcode(unsigned Opc,
return AArch64::LDRWui;
case AArch64::LDURSWi:
return AArch64::LDURWi;
- case AArch64::LDRSWpre:
- return AArch64::LDRWpre;
}
}
@@ -374,8 +372,6 @@ static unsigned getMatchingPairOpcode(unsigned Opc) {
case AArch64::LDRSWui:
case AArch64::LDURSWi:
return AArch64::LDPSWi;
- case AArch64::LDRSWpre:
- return AArch64::LDPSWpre;
}
}
@@ -589,8 +585,6 @@ static bool isPreLdStPairCandidate(MachineInstr &FirstMI, MachineInstr &MI) {
return (OpcB == AArch64::LDRWui) || (OpcB == AArch64::LDURWi);
case AArch64::LDRXpre:
return (OpcB == AArch64::LDRXui) || (OpcB == AArch64::LDURXi);
- case AArch64::LDRSWpre:
- return (OpcB == AArch64::LDRSWui) || (OpcB == AArch64::LDURSWi);
}
}
@@ -1346,7 +1340,7 @@ static bool areCandidatesToMergeOrPair(MachineInstr &FirstMI, MachineInstr &MI,
return false;
// The STR<S,D,Q,W,X>pre - STR<S,D,Q,W,X>ui and
- // LDR<S,D,Q,W,X,SW>pre-LDR<S,D,Q,W,X,SW>ui
+ // LDR<S,D,Q,W,X>pre-LDR<S,D,Q,W,X>ui
// are candidate pairs that can be merged.
if (isPreLdStPairCandidate(FirstMI, MI))
return true;
diff --git a/llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir b/llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
index 906cac048136ea..c0d0d2b441be46 100644
--- a/llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
+++ b/llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
@@ -588,7 +588,7 @@ body: |
---
-name: 21-ldrswpre-ldrswui-merge
+name: 21-ldrswpre-ldrswui-no-merge
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
@@ -599,9 +599,10 @@ machineFunctionInfo:
body: |
bb.0:
liveins: $x0, $x1, $x2
- ; CHECK-LABEL: name: 21-ldrswpre-ldrswui-merge
+ ; CHECK-LABEL: name: 21-ldrswpre-ldrswui-no-merge
; CHECK: liveins: $x0, $x1, $x2
- ; CHECK: early-clobber $x1, renamable $x0, renamable $x2 = LDPSWpre renamable $x1, 10 :: (load (s32))
+ ; CHECK: early-clobber renamable $x1, renamable $x0 = LDRSWpre renamable $x1, 40, implicit $w1 :: (load (s32))
+ ; CHECK: renamable $x2 = LDRSWui renamable $x1, 1 :: (load (s32))
; CHECK: STPXi renamable $x0, renamable $x2, renamable $x1, 0 :: (store (s64))
; CHECK: RET undef $lr
early-clobber renamable $x1, renamable $x0 = LDRSWpre killed renamable $x1, 40 :: (load (s32))
@@ -613,7 +614,7 @@ body: |
---
-name: 22-ldrswpre-ldurswi-merge
+name: 22-ldrswpre-ldurswi-no-merge
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
@@ -624,9 +625,10 @@ machineFunctionInfo:
body: |
bb.0:
liveins: $x0, $x1, $x2
- ; CHECK-LABEL: name: 22-ldrswpre-ldurswi-merge
+ ; CHECK-LABEL: name: 22-ldrswpre-ldurswi-no-merge
; CHECK: liveins: $x0, $x1, $x2
- ; CHECK: early-clobber $x1, renamable $x0, renamable $x2 = LDPSWpre renamable $x1, 10 :: (load (s32))
+ ; CHECK: early-clobber renamable $x1, renamable $x0 = LDRSWpre renamable $x1, 40, implicit $w1 :: (load (s32))
+ ; CHECK: renamable $x2 = LDURSWi renamable $x1, 4 :: (load (s32))
; CHECK: STPXi renamable $x0, renamable $x2, renamable $x1, 0 :: (store (s64))
; CHECK: RET undef $lr
early-clobber renamable $x1, renamable $x0 = LDRSWpre killed renamable $x1, 40 :: (load (s32))
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