[PATCH] D155299: [AArch64][SVE2] Combine add+lsr to rshrnb for stores

Kerry McLaughlin via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Jul 25 09:01:13 PDT 2023


kmclaughlin added a comment.

Thank you for adding the new tests @MattDevereau, I just have a couple of small suggestions in the trySimplifySrlAddToRshrnb function.



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:20096
+
+  auto SrlOp1 = dyn_cast<ConstantSDNode>(DAG.getSplatValue(Srl->getOperand(1)));
+  if (!SrlOp1)
----------------
I think if you change this to `dyn_cast_or_null` you can remove the additional `isSplatValue` check at the beginning of the function.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:20105
+    return SDValue();
+  auto AddOp1 = dyn_cast<ConstantSDNode>(DAG.getSplatValue(Add->getOperand(1)));
+  if (!AddOp1)
----------------
Similarly here, I think you can remove the `isSplatValue` above by using `dyn_cast_or_null`


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155299/new/

https://reviews.llvm.org/D155299



More information about the llvm-commits mailing list