[PATCH] D154488: [PowerPC] Define SchedModel for Power8

[Qiu Chaofan via Phabricator via llvm-commits]

qiucf added inline comments.


================
Comment at: llvm/test/CodeGen/PowerPC/atomics-regression.ll:456
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    clrlwi 4, 4, 24
 ; PPC64LE-NEXT:    lwsync
+; PPC64LE-NEXT:    clrlwi 4, 4, 24
----------------
shchenz wrote:
> Aren't the atomic related instructions are barriers to the scheduler? Can you check why there are changes around them? Thanks.
`lwsync` (`SYNC`) is treated as global memory barrier. But `clrlwi` (`RLWINM`) neither writes nor reads any memory, so scheduling such instruction around SYNC is okay. BTW, the new codegen is the original order.


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  https://reviews.llvm.org/D154488/new/

https://reviews.llvm.org/D154488