[PATCH] D153499: [RISCV] Add support for custom CSRs for Sifive S76.

[garvit gupta via Phabricator via llvm-commits]

garvitgupta08 updated this revision to Diff 534008.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153499/new/

https://reviews.llvm.org/D153499

Files:
  csr.patch
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVProcessors.td
  llvm/lib/Target/RISCV/RISCVSystemOperands.td
  llvm/test/MC/RISCV/xsfcie-invalid.s
  llvm/test/MC/RISCV/xsfcie-valid.s

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D153499.534008.patch
Type: text/x-patch
Size: 13136 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230623/73d63e36/attachment.bin>