[PATCH] D150824: [RISCV] Lower experimental_get_vector_length intrinsic to vsetvli for some cases.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:6524
+  assert(VF >= 1 && VF <= 64 && isPowerOf2_32(VF) && "Unexpected VF");
+
+  bool Fractional = VF < 8;
----------------
reames wrote:
> This depends very heavily on the fact that VLMAX for 1 x i8 and VLMAX for 1 x i64 are the same.  It took me a while to convince myself that this was actually true.  The former maps to a fractional lmul, the later maps to m1.  And as a result, the element width is irrelevant.
> 
> Can you add a comment which explains this in a bit more detail?  If this is already well explained elsewhere, you can simply point to that comment.  
A lot of this needs to be rewritten using RVVBitsPerBlock. I'll update.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150824/new/

https://reviews.llvm.org/D150824