[PATCH] D150824: [RISCV] Lower experimental_get_vector_length intrinsic to vsetvli for some cases.

[Philip Reames via Phabricator via llvm-commits]

reames accepted this revision.
reames added a comment.
This revision is now accepted and ready to land.

LGTM w/comment addressed.



================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:6524
+  assert(VF >= 1 && VF <= 64 && isPowerOf2_32(VF) && "Unexpected VF");
+
+  bool Fractional = VF < 8;
----------------
This depends very heavily on the fact that VLMAX for 1 x i8 and VLMAX for 1 x i64 are the same.  It took me a while to convince myself that this was actually true.  The former maps to a fractional lmul, the later maps to m1.  And as a result, the element width is irrelevant.

Can you add a comment which explains this in a bit more detail?  If this is already well explained elsewhere, you can simply point to that comment.  


Repository:
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  https://reviews.llvm.org/D150824/new/

https://reviews.llvm.org/D150824